Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.21			88.21

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_device	98.42			98.42

---

Module Instance : tb.dut.top_earlgrey.u_spi_device

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.42			98.42

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.42			98.42

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	61	50	81.97
Total Bits	424	374	88.21
Total Bits 0->1	212	187	88.21
Total Bits 1->0	212	187	88.21

Ports	61	50	81.97
Port Bits	424	374	88.21
Port Bits 0->1	212	187	88.21
Port Bits 1->0	212	187	88.21

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[12:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	INPUT
tl_o.a_ready	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T78,T151	Yes	T70,T72,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T10,*T73,*T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T191	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T191	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	OUTPUT
cio_sck_i	Yes	Yes	T10,T39,T40	Yes	T10,T7,T39	INPUT
cio_csb_i	Yes	Yes	T10,T7,T11	Yes	T10,T7,T11	INPUT
cio_sd_o[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T10,T12,T194	Yes	T10,T12,T194	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T39,T40	Yes	T10,T39,T40	INPUT
cio_tpm_csb_i	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T39,T40	Yes	T10,T39,T40	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T10,T7,T11	Yes	T10,T7,T11	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T10,T39,T40	Yes	T10,T7,T39	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T10,T194,T212	Yes	T10,T11,T12	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T10,T152,T153	Yes	T10,T152,T153	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T152,T39,T40	Yes	T152,T39,T40	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
sck_monitor_o	Yes	Yes	T10,T39,T40	Yes	T10,T7,T39	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_device

	Total	Covered	Percent
Totals	51	50	98.04
Total Bits	380	374	98.42
Total Bits 0->1	190	187	98.42
Total Bits 1->0	190	187	98.42

Ports	51	50	98.04
Port Bits	380	374	98.42
Port Bits 0->1	190	187	98.42
Port Bits 1->0	190	187	98.42

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[12:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	INPUT
tl_o.a_ready	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T78,T151	Yes	T70,T72,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T10,*T73,*T152	Yes	T10,T73,T152	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T191	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T191	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	OUTPUT
cio_sck_i	Yes	Yes	T10,T39,T40	Yes	T10,T7,T39	INPUT
cio_csb_i	Yes	Yes	T10,T7,T11	Yes	T10,T7,T11	INPUT
cio_sd_o[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T10,T12,T194	Yes	T10,T12,T194	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T39,T40	Yes	T10,T39,T40	INPUT
cio_tpm_csb_i	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T39,T40	Yes	T10,T39,T40	OUTPUT
passthrough_o.csb_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.csb	Yes	Yes	T10,T7,T11	Yes	T10,T7,T11	OUTPUT
passthrough_o.sck_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.sck	Yes	Yes	T10,T39,T40	Yes	T10,T7,T39	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T10,T194,T212	Yes	T10,T11,T12	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T10,T152,T153	Yes	T10,T152,T153	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T152,T39,T40	Yes	T152,T39,T40	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sck_monitor_o	Yes	Yes	T10,T39,T40	Yes	T10,T7,T39	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range