Unified Coverage Report :: Module :: ibex_top

Module : ibex_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.40			94.40

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core	96.76			96.76

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76			96.76

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76			96.76

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.55	95.29	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : ibex_top

	Total	Covered	Percent
Totals	40	34	85.00
Total Bits	822	776	94.40
Total Bits 0->1	411	388	94.40
Total Bits 1->0	411	388	94.40

Ports	40	34	85.00
Port Bits	822	776	94.40
Port Bits 0->1	411	388	94.40
Port Bits 1->0	411	388	94.40

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
instr_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
instr_addr_o[27:17]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	*T234,*T173,*T175	Yes	T234,T173,T175	OUTPUT
instr_addr_o[30]	No	No		No		OUTPUT
instr_addr_o[31]	Yes	Yes	T174,T176,T287	Yes	T174,T176,T287	OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_err_i	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
data_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_we_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_be_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_err_i	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
irq_software_i	Yes	Yes	T243,T244,T245	Yes	T243,T244,T245	INPUT
irq_timer_i	Yes	Yes	T246,T152,T153	Yes	T246,T152,T153	INPUT
irq_external_i	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
scramble_key_valid_i	Yes	Yes	T174,T176,T177	Yes	T174,T176,T177	INPUT
scramble_key_i[127:0]	Yes	Yes	T1,T2,T84	Yes	T1,T2,T84	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T1,T3,T85	Yes	T1,T2,T3	INPUT
scramble_req_o	Yes	Yes	T173,T174,T175	Yes	T173,T174,T175	OUTPUT
debug_req_i	Yes	Yes	T249,T250,T251	Yes	T249,T250,T251	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T236,T237,T238	Yes	T236,T237,T238	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
alert_minor_o	Yes	Yes	T356	Yes	T356	OUTPUT
alert_major_internal_o	Yes	Yes	T357,T358	Yes	T356,T357,T358	OUTPUT
alert_major_bus_o	Yes	Yes	T234,T118,T235	Yes	T234,T118,T235	OUTPUT
core_sleep_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

	Total	Covered	Percent
Totals	36	34	94.44
Total Bits	802	776	96.76
Total Bits 0->1	401	388	96.76
Total Bits 1->0	401	388	96.76

Ports	36	34	94.44
Port Bits	802	776	96.76
Port Bits 0->1	401	388	96.76
Port Bits 1->0	401	388	96.76

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
instr_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
instr_addr_o[27:17]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	*T234,*T173,*T175	Yes	T234,T173,T175	OUTPUT
instr_addr_o[30]	No	No		No		OUTPUT
instr_addr_o[31]	Yes	Yes	T174,T176,T287	Yes	T174,T176,T287	OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_err_i	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
data_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_we_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_be_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_err_i	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
irq_software_i	Yes	Yes	T243,T244,T245	Yes	T243,T244,T245	INPUT
irq_timer_i	Yes	Yes	T246,T152,T153	Yes	T246,T152,T153	INPUT
irq_external_i	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
scramble_key_valid_i	Yes	Yes	T174,T176,T177	Yes	T174,T176,T177	INPUT
scramble_key_i[127:0]	Yes	Yes	T1,T2,T84	Yes	T1,T2,T84	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T1,T3,T85	Yes	T1,T2,T3	INPUT
scramble_req_o	Yes	Yes	T173,T174,T175	Yes	T173,T174,T175	OUTPUT
debug_req_i	Yes	Yes	T249,T250,T251	Yes	T249,T250,T251	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T236,T237,T238	Yes	T236,T237,T238	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
alert_minor_o	Yes	Yes	T356	Yes	T356	OUTPUT
alert_major_internal_o	Yes	Yes	T357,T358	Yes	T356,T357,T358	OUTPUT
alert_major_bus_o	Yes	Yes	T234,T118,T235	Yes	T234,T118,T235	OUTPUT
core_sleep_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range