Line Coverage for Module :
prim_lc_or_hardened
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' or '../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
4 |
4 |
60 |
1 |
1 |
Cond Coverage for Module :
prim_lc_or_hardened
| Total | Covered | Percent |
Conditions | 28 | 28 | 100.00 |
Logical | 28 | 28 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 56
EXPRESSION ((lc_en_a_copies[0] == ActVal) || (lc_en_b_copies[0] == ActVal))
--------------1-------------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_a_copies[0] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_b_copies[0] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
EXPRESSION ((lc_en_a_copies[1] == ActVal) || (lc_en_b_copies[1] == ActVal))
--------------1-------------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_a_copies[1] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_b_copies[1] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
EXPRESSION ((lc_en_a_copies[2] == ActVal) || (lc_en_b_copies[2] == ActVal))
--------------1-------------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_a_copies[2] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_b_copies[2] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
EXPRESSION ((lc_en_a_copies[3] == ActVal) || (lc_en_b_copies[3] == ActVal))
--------------1-------------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_a_copies[3] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 56
SUB-EXPRESSION (lc_en_b_copies[3] == ActVal)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_lc_or_hardened
Assertion Details
FunctionCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
97049996 |
96445242 |
0 |
0 |
T1 |
80216 |
79863 |
0 |
0 |
T2 |
33637 |
33163 |
0 |
0 |
T3 |
17259 |
16574 |
0 |
0 |
T13 |
147669 |
147275 |
0 |
0 |
T30 |
54264 |
53749 |
0 |
0 |
T31 |
40645 |
40087 |
0 |
0 |
T32 |
59800 |
59319 |
0 |
0 |
T61 |
58161 |
57647 |
0 |
0 |
T84 |
33847 |
33212 |
0 |
0 |
T85 |
142228 |
141509 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
97049996 |
96445242 |
0 |
0 |
T1 |
80216 |
79863 |
0 |
0 |
T2 |
33637 |
33163 |
0 |
0 |
T3 |
17259 |
16574 |
0 |
0 |
T13 |
147669 |
147275 |
0 |
0 |
T30 |
54264 |
53749 |
0 |
0 |
T31 |
40645 |
40087 |
0 |
0 |
T32 |
59800 |
59319 |
0 |
0 |
T61 |
58161 |
57647 |
0 |
0 |
T84 |
33847 |
33212 |
0 |
0 |
T85 |
142228 |
141509 |
0 |
0 |