Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386129876	40228569	0	0
DepthKnown_A	386129876	386033854	0	0
RvalidKnown_A	386129876	386033854	0	0
WreadyKnown_A	386129876	386033854	0	0
gen_passthru_fifo.paramCheckPass	893	893	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	40228569	0	0
T1	331211	46569	0	0
T2	136635	16812	0	0
T3	67522	6498	0	0
T13	590350	53687	0	0
T30	220870	28947	0	0
T31	163914	16743	0	0
T32	244079	32216	0	0
T61	237114	23710	0	0
T84	136843	15783	0	0
T85	588053	52334	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	893	893	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386129876	30921082	0	0
DepthKnown_A	386129876	386033854	0	0
RvalidKnown_A	386129876	386033854	0	0
WreadyKnown_A	386129876	386033854	0	0
gen_passthru_fifo.paramCheckPass	893	893	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	30921082	0	0
T1	331211	43334	0	0
T2	136635	14399	0	0
T3	67522	4815	0	0
T13	590350	49582	0	0
T30	220870	19162	0	0
T31	163914	13349	0	0
T32	244079	22375	0	0
T61	237114	16670	0	0
T84	136843	13088	0	0
T85	588053	48409	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	893	893	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386129876	23265673	0	0
DepthKnown_A	386129876	386033854	0	0
RvalidKnown_A	386129876	386033854	0	0
WreadyKnown_A	386129876	386033854	0	0
gen_passthru_fifo.paramCheckPass	893	893	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	23265673	0	0
T1	331211	40984	0	0
T2	136635	4640	0	0
T3	67522	3916	0	0
T13	590350	72434	0	0
T30	220870	13652	0	0
T31	163914	10518	0	0
T32	244079	15957	0	0
T61	237114	11369	0	0
T84	136843	7883	0	0
T85	588053	73177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	893	893	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	386129876	22922981	0	0
DepthKnown_A	386129876	386033854	0	0
RvalidKnown_A	386129876	386033854	0	0
WreadyKnown_A	386129876	386033854	0	0
gen_passthru_fifo.paramCheckPass	893	893	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	22922981	0	0
T1	331211	40828	0	0
T2	136635	4471	0	0
T3	67522	3805	0	0
T13	590350	72223	0	0
T30	220870	13264	0	0
T31	163914	10293	0	0
T32	244079	15569	0	0
T61	237114	11020	0	0
T84	136843	7730	0	0
T85	588053	72976	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386129876	386033854	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	893	893	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466564765	95594	0	0
DepthKnown_A	466564765	466456759	0	0
RvalidKnown_A	466564765	466456759	0	0
WreadyKnown_A	466564765	466456759	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	95594	0	0
T1	331211	13	0	0
T2	136635	47	0	0
T3	67522	13	0	0
T13	590350	56	0	0
T30	220870	151	0	0
T31	163914	26	0	0
T32	244079	151	0	0
T61	237114	102	0	0
T84	136843	18	0	0
T85	588053	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466564765	98740	0	0
DepthKnown_A	466564765	466456759	0	0
RvalidKnown_A	466564765	466456759	0	0
WreadyKnown_A	466564765	466456759	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	98740	0	0
T1	331211	13	0	0
T2	136635	47	0	0
T3	67522	13	0	0
T13	590350	56	0	0
T30	220870	151	0	0
T31	163914	26	0	0
T32	244079	151	0	0
T61	237114	102	0	0
T84	136843	18	0	0
T85	588053	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466564765	48826	0	0
DepthKnown_A	466564765	466456759	0	0
RvalidKnown_A	466564765	466456759	0	0
WreadyKnown_A	466564765	466456759	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	48826	0	0
T1	331211	12	0	0
T2	136635	46	0	0
T3	67522	12	0	0
T13	590350	55	0	0
T30	220870	95	0	0
T31	163914	24	0	0
T32	244079	95	0	0
T61	237114	94	0	0
T84	136843	17	0	0
T85	588053	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466564765	48826	0	0
DepthKnown_A	466564765	466456759	0	0
RvalidKnown_A	466564765	466456759	0	0
WreadyKnown_A	466564765	466456759	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	48826	0	0
T1	331211	12	0	0
T2	136635	46	0	0
T3	67522	12	0	0
T13	590350	55	0	0
T30	220870	95	0	0
T31	163914	24	0	0
T32	244079	95	0	0
T61	237114	94	0	0
T84	136843	17	0	0
T85	588053	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466564765	46768	0	0
DepthKnown_A	466564765	466456759	0	0
RvalidKnown_A	466564765	466456759	0	0
WreadyKnown_A	466564765	466456759	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	46768	0	0
T1	331211	1	0	0
T2	136635	1	0	0
T3	67522	1	0	0
T13	590350	1	0	0
T30	220870	56	0	0
T31	163914	2	0	0
T32	244079	56	0	0
T61	237114	8	0	0
T84	136843	1	0	0
T85	588053	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	466564765	49914	0	0
DepthKnown_A	466564765	466456759	0	0
RvalidKnown_A	466564765	466456759	0	0
WreadyKnown_A	466564765	466456759	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	49914	0	0
T1	331211	1	0	0
T2	136635	1	0	0
T3	67522	1	0	0
T13	590350	1	0	0
T30	220870	56	0	0
T31	163914	2	0	0
T32	244079	56	0	0
T61	237114	8	0	0
T84	136843	1	0	0
T85	588053	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466564765	466456759	0	0
T1	331211	331156	0	0
T2	136635	136584	0	0
T3	67522	67467	0	0
T13	590350	590295	0	0
T30	220870	220754	0	0
T31	163914	163801	0	0
T32	244079	243963	0	0
T61	237114	236994	0	0
T84	136843	136788	0	0
T85	588053	587998	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T61	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0