Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T85,T208,T43	Yes	T85,T208,T43	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T85,T208,T43	Yes	T85,T208,T43	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T85,T208,T43	Yes	T85,T208,T43	INPUT
tl_o.a_ready	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T73,*T75,*T49	Yes	T73,T75,T49	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T85,*T208,*T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T156,T621,T620	Yes	T156,T621,T620	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T156,T621,T620	Yes	T156,T621,T620	OUTPUT
cio_rx_i	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
intr_rx_watermark_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
intr_tx_empty_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
intr_rx_overflow_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T85,T208,T43	Yes	T85,T208,T43	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T85,T208,T43	Yes	T85,T208,T43	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T85,T208,T43	Yes	T85,T208,T43	INPUT
tl_o.a_ready	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_error	Yes	Yes	T70,T78,T77	Yes	T70,T71,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T73,*T75,*T49	Yes	T73,T75,T49	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T72,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T85,*T208,*T209	Yes	T85,T208,T209	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T156,T55,T56	Yes	T156,T55,T56	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T156,T55,T56	Yes	T156,T55,T56	OUTPUT
cio_rx_i	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
intr_rx_watermark_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
intr_tx_empty_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
intr_rx_overflow_o	Yes	Yes	T85,T208,T209	Yes	T85,T208,T209	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T306,T196,T197	Yes	T306,T196,T197	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T306,T196,T197	Yes	T306,T196,T197	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T156,T306,T196	Yes	T156,T306,T196	INPUT
tl_o.a_ready	Yes	Yes	T156,T306,T196	Yes	T156,T306,T196	OUTPUT
tl_o.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T306,T196,T197	Yes	T306,T196,T197	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T156,T306,T196	Yes	T156,T306,T196	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T156,T306,T196	Yes	T156,T306,T196	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T70,*T78	Yes	T75,T70,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T306,*T196,*T197	Yes	T306,T196,T197	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T156,T306,T196	Yes	T156,T306,T196	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T156,T55,T56	Yes	T156,T55,T56	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T156,T55,T56	Yes	T156,T55,T56	OUTPUT
cio_rx_i	Yes	Yes	T196,T33,T197	Yes	T7,T196,T33	INPUT
cio_tx_o	Yes	Yes	T196,T197,T206	Yes	T196,T197,T206	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T306,T196,T197	Yes	T306,T196,T197	OUTPUT
intr_rx_watermark_o	Yes	Yes	T306,T196,T197	Yes	T306,T196,T197	OUTPUT
intr_tx_empty_o	Yes	Yes	T306,T196,T197	Yes	T306,T196,T197	OUTPUT
intr_rx_overflow_o	Yes	Yes	T306,T196,T197	Yes	T306,T196,T197	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T306,T189,T190	Yes	T306,T189,T190	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T306,T189,T190	Yes	T306,T189,T190	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T156,T306,T55	Yes	T156,T306,T55	INPUT
tl_o.a_ready	Yes	Yes	T156,T306,T55	Yes	T156,T306,T55	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T76	Yes	T70,T71,T151	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T306,T189,T190	Yes	T306,T189,T190	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T156,T306,T189	Yes	T156,T306,T55	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T156,T306,T189	Yes	T156,T306,T55	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T70,*T71	Yes	T75,T70,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T306,*T189,*T190	Yes	T306,T189,T190	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T156,T306,T55	Yes	T156,T306,T55	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T156,T620,T295	Yes	T156,T620,T295	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T83,T627	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T83,T627	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T156,T620,T295	Yes	T156,T620,T295	OUTPUT
cio_rx_i	Yes	Yes	T189,T190,T317	Yes	T189,T190,T317	INPUT
cio_tx_o	Yes	Yes	T189,T190,T317	Yes	T189,T190,T317	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T306,T189,T190	Yes	T306,T189,T190	OUTPUT
intr_rx_watermark_o	Yes	Yes	T306,T189,T190	Yes	T306,T189,T190	OUTPUT
intr_tx_empty_o	Yes	Yes	T306,T189,T190	Yes	T306,T189,T190	OUTPUT
intr_rx_overflow_o	Yes	Yes	T306,T189,T190	Yes	T306,T189,T190	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T13,T14,T306	Yes	T13,T14,T306	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T13,T14,T306	Yes	T13,T14,T306	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T13,T156,T14	Yes	T13,T156,T14	INPUT
tl_o.a_ready	Yes	Yes	T13,T156,T14	Yes	T13,T156,T14	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T14,T306	Yes	T13,T14,T306	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T13,T156,T14	Yes	T13,T156,T14	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T13,T156,T14	Yes	T13,T156,T14	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T70,*T71	Yes	T75,T70,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T13,*T14,*T306	Yes	T13,T14,T306	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T13,T156,T14	Yes	T13,T156,T14	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T156,T621,T55	Yes	T156,T621,T55	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T156,T621,T55	Yes	T156,T621,T55	OUTPUT
cio_rx_i	Yes	Yes	T13,T14,T204	Yes	T13,T14,T204	INPUT
cio_tx_o	Yes	Yes	T13,T14,T204	Yes	T13,T14,T204	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T13,T14,T306	Yes	T13,T14,T306	OUTPUT
intr_rx_watermark_o	Yes	Yes	T13,T14,T306	Yes	T13,T14,T306	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T14,T306	Yes	T13,T14,T306	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T14,T306	Yes	T13,T14,T306	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T305,T320	Yes	T306,T305,T320	OUTPUT

*Tests covering at least one bit in the range