Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T72,T78,T241	Yes	T72,T78,T241	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T73,T74,T242	Yes	T73,T74,T242	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T73,T74,T242	Yes	T73,T74,T242	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T42,T66,T73	Yes	T42,T66,T73	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T42,T66,T73	Yes	T42,T66,T73	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T42,T66,T73	Yes	T42,T66,T73	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T42,T66,T73	Yes	T42,T66,T73	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T42,T66,T73	Yes	T42,T66,T73	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T42,T66,T73	Yes	T42,T66,T73	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T42,*T66,*T73	Yes	T42,T66,T73	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T42,T66,T73	Yes	T42,T66,T73	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T49,T70,T72	Yes	T49,T70,T72	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T49,T70,T71	Yes	T49,T70,T71	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T49,T70,T72	Yes	T49,T70,T72	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T49,*T70,*T72	Yes	T49,T70,T72	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T73,T249,T250	Yes	T73,T249,T250	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T249,T250	Yes	T73,T249,T250	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T73,T249,T250	Yes	T73,T249,T250	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T73,T249,T250	Yes	T73,T249,T250	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T73,T249,T250	Yes	T73,T249,T250	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T249,*T250,*T251	Yes	T249,T250,T251	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T73,T249,T250	Yes	T73,T249,T250	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T249,T250,T251	Yes	T249,T250,T251	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T249,T250	Yes	T73,T249,T250	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T249,*T250,*T251	Yes	T249,T250,T251	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T30,T31,T32	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T73,T249,T250	Yes	T73,T249,T250	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T74,T163,T178	Yes	T74,T163,T178	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T264,T265,T55	Yes	T264,T265,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T264,T265,T55	Yes	T264,T265,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T264,T265,T55	Yes	T264,T265,T55	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T49,*T70,*T71	Yes	T49,T70,T71	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T264,T265,T55	Yes	T264,T265,T55	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T264,T265,T55	Yes	T264,T265,T55	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T264,T265,T266	Yes	T264,T265,T266	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T70,T71	Yes	T55,T56,T57	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T264,T265,T266	Yes	T264,T265,T55	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T70,T71,T78	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T49,T70,T71	Yes	T49,T70,T71	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T264,*T265,*T266	Yes	T264,T265,T266	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T264,T265,T55	Yes	T264,T265,T55	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T30,T32,T187	Yes	T30,T32,T187	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T194,T212	Yes	T10,T194,T212	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T73,T152	Yes	T10,T73,T152	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T73,*T152	Yes	T10,T73,T152	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T156,T10,T73	Yes	T156,T10,T73	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T73,T152,T55	Yes	T73,T152,T55	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T73,T152,T55	Yes	T73,T152,T55	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T152,T55	Yes	T73,T152,T55	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T73,T152,T55	Yes	T73,T152,T55	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T73,T152,T55	Yes	T73,T152,T55	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T73,T152,T55	Yes	T73,T152,T55	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T73,T152,T55	Yes	T73,T152,T55	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T73,T152,T55	Yes	T73,T152,T55	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T73,T152,T351	Yes	T73,T152,T351	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T152,T351	Yes	T73,T152,T55	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T73,T152,T351	Yes	T73,T152,T351	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T73,*T152,*T351	Yes	T73,T152,T351	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T73,T152,T55	Yes	T73,T152,T55	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T75,*T70,*T72	Yes	T75,T70,T72	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T70,T78,T76	Yes	T70,T78,T76	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T70,T78,T76	Yes	T70,T78,T76	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T16,T17,T306	Yes	T16,T17,T306	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T17,T306	Yes	T16,T17,T306	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T75,*T70,*T78	Yes	T75,T70,T72	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T70,T78,T76	Yes	T70,T78,T76	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T70,T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T70,*T71,*T78	Yes	T70,T71,T78	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T3,T84,T30	Yes	T3,T84,T30	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T84,T30,T31	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T84,T636,T248	Yes	T84,T636,T248	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T84,T636,T248	Yes	T84,T636,T248	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T84,T186,T636	Yes	T84,T186,T636	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T84,T636,T248	Yes	T84,T636,T248	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T84,T186,T636	Yes	T84,T186,T636	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T84,T636,T327	Yes	T84,T636,T327	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T84,T186,T636	Yes	T84,T186,T636	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T84,T186,T636	Yes	T84,T186,T636	INPUT
tl_hmac_i.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T84,T186,T636	Yes	T84,T186,T636	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T84,T186,T636	Yes	T84,T186,T636	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T84,T636,T248	Yes	T84,T636,T248	INPUT
tl_hmac_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T84,*T636,*T248	Yes	T84,T636,T248	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T84,T186,T636	Yes	T84,T186,T636	INPUT
tl_kmac_o.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T423,T94,T124	Yes	T423,T94,T124	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T186,T423,T150	Yes	T186,T423,T150	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T186,T423,T150	Yes	T186,T423,T150	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T423,T94,T124	Yes	T423,T94,T124	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T186,T423,T150	Yes	T186,T423,T150	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T423,T94,T104	Yes	T423,T94,T104	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T186,T423,T150	Yes	T186,T423,T150	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T186,T423,T150	Yes	T186,T423,T150	INPUT
tl_kmac_i.d_error	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T186,T423,T150	Yes	T186,T423,T150	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T186,T423,T150	Yes	T186,T423,T150	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T423,T150,T94	Yes	T423,T94,T124	INPUT
tl_kmac_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T78	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T78	Yes	T70,T71,T72	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T423,*T150,*T94	Yes	T423,T94,T124	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T186,T423,T150	Yes	T186,T423,T150	INPUT
tl_aes_o.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T117,T125,T114	Yes	T117,T125,T114	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T117,T125,T114	Yes	T117,T125,T114	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T186,T117,T125	Yes	T186,T117,T125	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T117,T125,T114	Yes	T117,T125,T114	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T186,T117,T125	Yes	T186,T117,T125	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T186,T117,T125	Yes	T186,T117,T125	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T186,T117,T125	Yes	T186,T117,T125	INPUT
tl_aes_i.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T71,T72	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T186,T117,T125	Yes	T186,T117,T125	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T117,T125,T114	Yes	T117,T125,T114	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T186,T117,T125	Yes	T186,T117,T125	INPUT
tl_aes_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T71,T72	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T72,T78	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T186,*T117,*T125	Yes	T186,T117,T125	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T186,T117,T125	Yes	T186,T117,T125	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T71,T72	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T72,T78	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T1,*T113,*T248	Yes	T1,T113,T248	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T70,T71,T78	Yes	T70,T71,T72	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T78	Yes	T70,T71,T72	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T1,*T113,*T248	Yes	T1,T113,T248	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T70,T78,T76	Yes	T70,T78,T76	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T70,T78,T77	Yes	T70,T78,T77	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T70,T78,T76	Yes	T70,T72,T78	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T78,T76	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T70,*T78,*T77	Yes	T70,T78,T76	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T70,T78,T76	Yes	T70,T71,T78	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T1,*T113,*T248	Yes	T1,T113,T248	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_edn1_i.d_error	Yes	Yes	T70,T78,T77	Yes	T70,T72,T78	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_edn1_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T70,*T78,*T76	Yes	T70,T72,T78	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T70,T78,T76	Yes	T70,T72,T78	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T1,*T113,*T248	Yes	T1,T113,T248	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T70,T71,T78	Yes	T70,T71,T78	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T30,*T32,*T13	Yes	T30,T32,T13	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T30,T32,T13	Yes	T30,T32,T13	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T186,T113	Yes	T1,T186,T113	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T1,T186,T113	Yes	T1,T186,T113	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T1,T186,T113	Yes	T1,T186,T113	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T74,*T420,*T242	Yes	T74,T420,T242	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T1,T186,T113	Yes	T1,T186,T113	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T1,T186,T113	Yes	T1,T186,T113	INPUT
tl_otbn_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	INPUT
tl_otbn_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T74,*T420,*T242	Yes	T74,T420,T242	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T1,*T113,*T125	Yes	T1,T113,T125	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T44,T43,T213	Yes	T44,T43,T213	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T43,T150	Yes	T44,T43,T150	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T44,T43,T150	Yes	T44,T43,T150	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T43,T213,T114	Yes	T43,T213,T114	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T44,T43,T150	Yes	T44,T43,T150	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T44,T43,T150	Yes	T44,T43,T150	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T44,T43,T150	Yes	T44,T43,T150	INPUT
tl_keymgr_i.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T43,T213,T114	Yes	T43,T213,T114	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T43,T213	Yes	T44,T43,T213	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T44,T43,T213	Yes	T44,T43,T213	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T72,T78	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T72,T78	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T43,*T213,*T114	Yes	T44,T43,T150	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T44,T43,T150	Yes	T44,T43,T150	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T49,*T70,*T72	Yes	T49,T70,T72	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T49,T70,T72	Yes	T49,T70,T72	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T49,*T70,*T72	Yes	T49,T70,T72	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T118,T73,T173	Yes	T118,T73,T173	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T285,T118,T73	Yes	T285,T118,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T285,T118,T73	Yes	T285,T118,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T118,T73,T173	Yes	T118,T73,T173	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T285,T118,T73	Yes	T285,T118,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T285,T118,T73	Yes	T285,T118,T73	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T285,T118,T73	Yes	T285,T118,T73	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T70,T78,T76	Yes	T70,T72,T78	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T73,T173,T175	Yes	T73,T173,T175	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T118,T73,T173	Yes	T118,T73,T173	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T118,T73,T173	Yes	T118,T73,T173	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T73,*T49,*T70	Yes	T73,T49,T70	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T118,*T73,*T173	Yes	T285,T118,T73	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T285,T118,T73	Yes	T285,T118,T73	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range