Unified Coverage Report :: Module :: pwrmgr

Module : pwrmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pwrmgr_aon	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pwrmgr_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pwrmgr

	Total	Covered	Percent
Totals	83	83	100.00
Total Bits	460	460	100.00
Total Bits 0->1	230	230	100.00
Total Bits 1->0	230	230	100.00

Ports	83	83	100.00
Port Bits	460	460	100.00
Port Bits 0->1	230	230	100.00
Port Bits 1->0	230	230	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_slow_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_slow_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T186,T58	Yes	T32,T186,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T186,T58	Yes	T32,T186,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[21:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T75	Yes	T73,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T74,T75	Yes	T73,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T32,T186,T58	Yes	T32,T186,T58	INPUT
tl_o.a_ready	Yes	Yes	T32,T186,T58	Yes	T32,T186,T58	OUTPUT
tl_o.d_error	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T32,T186,T58	Yes	T32,T186,T58	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T186,T58,T247	Yes	T186,T58,T247	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T32,T186,T58	Yes	T32,T186,T58	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T49,*T70,*T72	Yes	T49,T70,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T72,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T186,*T58,*T19	Yes	T32,T186,T58	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T32,T186,T58	Yes	T32,T186,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T32,T247,T188	Yes	T32,T247,T188	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T32,T247,T188	Yes	T32,T247,T188	OUTPUT
pwr_ast_i.main_pok	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwr_ast_i.usb_clk_val	Yes	Yes	T13,T58,T4	Yes	T1,T2,T3	INPUT
pwr_ast_i.io_clk_val	Yes	Yes	T13,T58,T4	Yes	T1,T2,T3	INPUT
pwr_ast_i.core_clk_val	Yes	Yes	T13,T58,T4	Yes	T1,T2,T3	INPUT
pwr_ast_i.slow_clk_val	Yes	Yes	T13,T65,T97	Yes	T1,T2,T3	INPUT
pwr_ast_o.usb_clk_en	Yes	Yes	T58,T4,T59	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.io_clk_en	Yes	Yes	T58,T4,T59	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.core_clk_en	Yes	Yes	T58,T4,T59	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.slow_clk_en	Unreachable	Unreachable		Unreachable		OUTPUT
pwr_ast_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwr_ast_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwr_ast_o.main_pd_n	Yes	Yes	T20,T122,T123	Yes	T20,T122,T123	OUTPUT
pwr_rst_i.rst_sys_src_n[1:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
pwr_rst_i.rst_lc_src_n[1:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
pwr_rst_o.reset_cause[1:0]	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	OUTPUT
pwr_rst_o.rstreqs[4:0]	Yes	Yes	T19,T188,T20	Yes	T19,T188,T20	OUTPUT
pwr_rst_o.rst_sys_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	OUTPUT
pwr_rst_o.rst_lc_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	OUTPUT
pwr_clk_o.usb_ip_clk_en	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.io_ip_clk_en	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.main_ip_clk_en	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
pwr_clk_i.usb_status	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
pwr_clk_i.io_status	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
pwr_clk_i.main_status	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
pwr_otp_i.otp_idle	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
pwr_otp_i.otp_done	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_lc_i.lc_idle	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
pwr_lc_i.lc_done	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_flash_i.flash_idle	Yes	Yes	T4,T6,T124	Yes	T4,T6,T124	INPUT
pwr_cpu_i.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
fetch_en_o[3:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	OUTPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
wakeups_i[5:0]	Yes	Yes	T19,T188,T20	Yes	T19,T188,T20	INPUT
rstreqs_i[1:0]	Yes	Yes	T19,T188,T20	Yes	T19,T188,T20	INPUT
ndmreset_req_i	Yes	Yes	T44,T48,T249	Yes	T44,T48,T249	INPUT
strap_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
low_power_o	Yes	Yes	T1,T2,T3	Yes	T58,T4,T59	OUTPUT
rom_ctrl_i.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	INPUT
rom_ctrl_i.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T30,T31,T32	INPUT
sw_rst_req_i[3:0]	Yes	Yes	T2,T31,T4	Yes	T31,T4,T188	INPUT
esc_rst_tx_i.esc_n	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
esc_rst_tx_i.esc_p	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	INPUT
esc_rst_rx_o.resp_n	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	OUTPUT
esc_rst_rx_o.resp_p	Yes	Yes	T30,T32,T61	Yes	T30,T32,T61	OUTPUT
intr_wakeup_o	Yes	Yes	T58,T59,T193	Yes	T58,T59,T193	OUTPUT

*Tests covering at least one bit in the range