Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.42			99.42

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_edn1	99.30			99.30
tb.dut.top_earlgrey.u_edn0	99.34			99.34

---

Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.30			99.30

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.30			99.30

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.34			99.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.34			99.34

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	78	74	94.87
Total Bits	1208	1201	99.42
Total Bits 0->1	604	602	99.67
Total Bits 1->0	604	599	99.17

Ports	78	74	94.87
Port Bits	1208	1201	99.42
Port Bits 0->1	604	602	99.67
Port Bits 1->0	604	599	99.17

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:16]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T70,T78,T76	Yes	T70,T72,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T78,*T76	Yes	T70,T72,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T78,T76	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T113,*T248	Yes	T1,T113,T248	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T113,T43,T125	Yes	T113,T43,T125	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[3].edn_req	Yes	Yes	T114,T424,T425	Yes	T114,T424,T425	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[7].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T113,T43,T125	Yes	T113,T43,T125	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T125,T126,T110	Yes	T113,T125,T114	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T113,T43,T125	Yes	T113,T43,T125	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T1,T113,T115	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T84,T30	Yes	T1,T2,T3	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T110,T111,T112	Yes	T113,T114,T115	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T114,T424,T426	Yes	T114,T424,T425	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T114,T424,T425	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T114,T424,T425	Yes	T114,T424,T425	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T30,T32,T186	Yes	T84,T30,T32	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T115,T103,T601	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T125,T364,T602	Yes	T125,T114,T424	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T125,T126,T110	Yes	T1,T113,T125	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T30,T61,T186	Yes	T2,T30,T13	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T125,T126,T110	Yes	T125,T114,T126	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T126,T112,T603	Yes	T1,T113,T125	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T125,T110,T294	Yes	T125,T110,T294	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T298,T55,T157	Yes	T298,T55,T157	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T157,T81,T82	Yes	T157,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T157,T81,T82	Yes	T157,T81,T82	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T55,T604,T56	Yes	T55,T604,T56	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T298,T55,T157	Yes	T298,T55,T157	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T55,T604,T56	Yes	T55,T604,T56	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T248,T314,T303	Yes	T248,T314,T303	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T248,T303,T304	Yes	T248,T303,T304	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1

	Total	Covered	Percent
Totals	50	48	96.00
Total Bits	712	707	99.30
Total Bits 0->1	356	354	99.44
Total Bits 1->0	356	353	99.16

Ports	50	48	96.00
Port Bits	712	707	99.30
Port Bits 0->1	356	354	99.44
Port Bits 1->0	356	353	99.16

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:19]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T1,*T113,*T248	Yes	T1,T113,T248	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T113,*T248	Yes	T1,T113,T248	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	INPUT
tl_i.a_valid	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_o.a_ready	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_o.d_error	Yes	Yes	T70,T78,T77	Yes	T70,T72,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T72,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T78,*T76	Yes	T70,T72,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T78,T76	Yes	T70,T72,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T113,*T248	Yes	T1,T113,T248	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
edn_i[0].edn_req	Yes	Yes	T113,T125,T114	Yes	T113,T125,T114	INPUT
edn_i[1].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[2].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[3].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[4].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[5].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[6].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[7].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_o[0].edn_bus[31:0]	Yes	Yes	T113,T125,T114	Yes	T113,T125,T114	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T125,T126,T110	Yes	T113,T125,T114	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T113,T125,T114	Yes	T113,T125,T114	OUTPUT
edn_o[1].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T113,T125,T114	Yes	T1,T113,T125	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T113,T125,T114	Yes	T1,T113,T125	INPUT
csrng_cmd_i.genbits_fips	No	No		Yes	T126,T603,T605	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T113,T125	Yes	T1,T113,T125	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T125,T110,T294	Yes	T125,T110,T294	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T55,T604,T56	Yes	T55,T604,T56	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T55,T604,T56	Yes	T55,T604,T56	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T248,T314,T303	Yes	T248,T314,T303	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T248,T303,T304	Yes	T248,T303,T304	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0

	Total	Covered	Percent
Totals	78	73	93.59
Total Bits	1206	1198	99.34
Total Bits 0->1	603	601	99.67
Total Bits 1->0	603	597	99.00

Ports	78	73	93.59
Port Bits	1206	1198	99.34
Port Bits 0->1	603	601	99.67
Port Bits 1->0	603	597	99.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T30,T31,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T78	Yes	T70,T72,T78	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T78,T76	Yes	T70,T78,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T78,T77	Yes	T70,T78,T77	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T70,T78,T76	Yes	T70,T72,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T113,T248	Yes	T1,T113,T248	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T72,T78	Yes	T70,T78,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T78,*T77	Yes	T70,T78,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T78,T76	Yes	T70,T71,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T113,*T248	Yes	T1,T113,T248	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T43,T213,T114	Yes	T43,T213,T114	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[3].edn_req	Yes	Yes	T114,T424,T425	Yes	T114,T424,T425	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[7].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T43,T213,T114	Yes	T43,T213,T114	OUTPUT
edn_o[0].edn_fips	No	No		Yes	T114,T119,T214	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T43,T213,T114	Yes	T43,T213,T114	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T1,T113,T115	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T84,T30	Yes	T1,T2,T3	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T110,T111,T112	Yes	T113,T114,T115	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T114,T424,T426	Yes	T114,T424,T425	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T114,T424,T425	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T114,T424,T425	Yes	T114,T424,T425	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T30,T32,T186	Yes	T84,T30,T32	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T115,T103,T601	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T125,T364,T602	Yes	T125,T114,T424	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T125,T126,T110	Yes	T1,T113,T125	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T30,T61,T186	Yes	T2,T30,T13	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T125,T126,T110	Yes	T125,T114,T126	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T30,T31	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T126,T112,T603	Yes	T1,T113,T125	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T125,T110,T294	Yes	T125,T110,T294	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T298,T55,T157	Yes	T298,T55,T157	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T157,T81,T82	Yes	T157,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T157,T81,T82	Yes	T157,T81,T82	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T298,T55,T157	Yes	T298,T55,T157	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T55,T56,T81	Yes	T55,T56,T81	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T248,T314,T303	Yes	T248,T314,T303	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T248,T303,T304	Yes	T248,T303,T304	OUTPUT

*Tests covering at least one bit in the range