Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3717848	1			T74	445		T75	114		T76	13
values[2]	736482	1			T75	60		T76	11		T80	71
values[3]	110638	1			T76	11		T224	6		T123	70
values[4]	58701	1			T76	11		T224	6		T123	59
values[5]	39426	1			T76	11		T224	6		T123	17
values[6]	29661	1			T76	11		T224	6		T123	4
values[7]	23451	1			T76	11		T224	6		T123	3
values[8]	20274	1			T76	11		T224	6		T791	5
values[9]	17971	1			T76	11		T224	6		T791	7
values[10]	16400	1			T76	12		T224	6		T791	1
values[11]	15537	1			T76	11		T224	6		T476	4
values[12]	14739	1			T76	11		T224	6		T476	6
values[13]	13929	1			T76	11		T224	6		T476	4
values[14]	13189	1			T76	11		T224	6		T476	5
values[15]	12889	1			T76	11		T224	6		T476	3
values[16]	12401	1			T76	11		T224	7		T476	1
values[17]	11966	1			T76	11		T224	6		T476	2
values[18]	11345	1			T76	11		T224	6		T476	2
values[19]	10746	1			T76	11		T224	6		T476	4
values[20]	10313	1			T76	11		T224	6		T476	1
values[21]	10268	1			T76	12		T224	6		T476	1
values[22]	9924	1			T76	11		T224	6		T476	5
values[23]	9885	1			T76	11		T224	6		T475	9
values[24]	9390	1			T76	11		T224	6		T475	7
values[25]	8842	1			T76	11		T224	7		T475	6
values[26]	8625	1			T76	11		T224	6		T475	4
values[27]	8202	1			T76	11		T224	6		T475	5
values[28]	7774	1			T76	11		T224	6		T475	8
values[29]	7334	1			T76	11		T224	6		T475	9
values[30]	6599	1			T76	11		T224	6		T475	2
values[31]	6155	1			T76	11		T224	6		T475	3
values[32]	5735	1			T76	11		T224	6		T475	5
values[33]	5478	1			T76	11		T224	6		T475	11
values[34]	5245	1			T76	11		T224	6		T475	3
values[35]	4809	1			T76	11		T224	6		T475	6
values[36]	4484	1			T76	11		T224	6		T475	17
values[37]	4228	1			T76	11		T224	6		T475	7
values[38]	4026	1			T76	12		T224	6		T475	3
values[39]	3943	1			T76	11		T224	6		T475	2
values[40]	3821	1			T76	11		T224	6		T475	1
values[41]	3807	1			T76	11		T224	6		T475	1
values[42]	3624	1			T76	11		T224	6		T475	4
values[43]	3593	1			T76	11		T224	6		T475	1
values[44]	3499	1			T76	11		T224	6		T475	2
values[45]	3500	1			T76	11		T224	6		T475	2
values[46]	3380	1			T76	11		T224	6		T475	1
values[47]	3236	1			T76	12		T224	6		T475	1
values[48]	3268	1			T76	11		T224	6		T475	1
values[49]	3087	1			T76	11		T224	6		T475	4
values[50]	3115	1			T76	11		T224	6		T475	5
values[51]	2989	1			T76	11		T224	6		T475	2
values[52]	2923	1			T76	11		T224	6		T475	2
values[53]	2727	1			T76	11		T224	6		T475	2
values[54]	2774	1			T76	11		T224	6		T475	6
values[55]	2675	1			T76	11		T224	6		T475	7
values[56]	2589	1			T76	11		T224	6		T475	4
values[57]	2489	1			T76	11		T224	6		T475	3
values[58]	2611	1			T76	11		T224	7		T475	2
values[59]	2751	1			T76	11		T224	6		T475	1
values[60]	2604	1			T76	11		T224	6		T475	3
values[61]	2869	1			T76	11		T224	6		T475	6
values[62]	4551	1			T76	11		T224	6		T475	18
values[63]	18061	1			T76	13		T224	7		T475	13
values[64]	223978	1			T76	1961		T224	1041		T475	61

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4800064	1			T74	442		T75	139		T76	1843
values[2]	791926	1			T75	32		T76	528		T80	230
values[3]	78112	1			T75	7		T76	142		T80	36
values[4]	14913	1			T76	44		T80	3		T224	19
values[5]	5833	1			T76	12		T224	10		T791	1
values[6]	3735	1			T76	6		T224	5		T791	2
values[7]	2947	1			T76	2		T224	3		T791	1
values[8]	2458	1			T76	1		T224	2		T475	20
values[9]	2013	1			T224	2		T475	8		T488	8
values[10]	1857	1			T224	2		T475	2		T488	1
values[11]	1834	1			T224	2		T488	2		T604	2
values[12]	1721	1			T224	2		T604	2		T585	1
values[13]	1583	1			T224	2		T604	2		T585	1
values[14]	1419	1			T224	2		T604	2		T585	1
values[15]	1239	1			T224	2		T604	2		T585	2
values[16]	1145	1			T224	2		T604	2		T585	1
values[17]	1084	1			T224	2		T604	2		T585	2
values[18]	1025	1			T224	2		T604	2		T585	2
values[19]	992	1			T224	2		T604	2		T585	2
values[20]	961	1			T224	2		T604	4		T585	1
values[21]	852	1			T224	2		T604	2		T585	9
values[22]	814	1			T224	2		T604	2		T585	2
values[23]	803	1			T224	2		T604	2		T585	4
values[24]	777	1			T224	2		T604	2		T585	2
values[25]	724	1			T224	2		T604	2		T585	1
values[26]	738	1			T224	2		T604	2		T585	1
values[27]	684	1			T224	2		T604	3		T585	3
values[28]	665	1			T224	2		T604	2		T585	6
values[29]	641	1			T224	2		T604	2		T585	1
values[30]	600	1			T224	2		T604	2		T585	1
values[31]	589	1			T224	2		T604	2		T585	1
values[32]	564	1			T224	2		T604	2		T585	2
values[33]	581	1			T224	2		T604	2		T585	1
values[34]	526	1			T224	2		T604	2		T585	2
values[35]	560	1			T224	2		T604	2		T585	4
values[36]	529	1			T224	2		T604	2		T585	2
values[37]	520	1			T224	2		T604	2		T585	1
values[38]	449	1			T224	2		T604	2		T585	2
values[39]	438	1			T224	2		T604	2		T585	1
values[40]	413	1			T224	2		T604	2		T585	1
values[41]	454	1			T224	2		T604	2		T585	2
values[42]	468	1			T224	2		T604	2		T585	2
values[43]	453	1			T224	2		T604	2		T585	1
values[44]	402	1			T224	2		T604	1		T585	1
values[45]	406	1			T224	2		T604	1		T585	2
values[46]	408	1			T224	2		T604	2		T585	1
values[47]	394	1			T224	2		T604	2		T585	1
values[48]	440	1			T224	3		T604	2		T585	4
values[49]	442	1			T224	2		T604	1		T585	2
values[50]	413	1			T224	2		T604	1		T585	3
values[51]	383	1			T224	2		T604	2		T585	4
values[52]	372	1			T224	2		T604	2		T585	3
values[53]	347	1			T224	2		T604	2		T585	2
values[54]	380	1			T224	2		T604	2		T585	1
values[55]	372	1			T224	2		T604	2		T585	2
values[56]	311	1			T224	2		T604	2		T585	1
values[57]	307	1			T224	2		T604	1		T585	2
values[58]	338	1			T224	2		T604	1		T585	2
values[59]	335	1			T224	2		T604	2		T585	2
values[60]	366	1			T224	2		T604	2		T585	1
values[61]	377	1			T224	2		T604	2		T585	1
values[62]	630	1			T224	2		T604	4		T585	1
values[63]	2835	1			T224	23		T604	4		T585	6
values[64]	23930	1			T224	353		T604	148		T585	74

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	614296	1			T74	521		T75	2		T76	12
values[2]	2629329	1			T75	76		T76	11		T80	344
values[3]	1166502	1			T75	48		T76	11		T80	282
values[4]	143131	1			T75	1		T76	11		T80	2
values[5]	74494	1			T76	11		T224	6		T123	44
values[6]	50120	1			T76	11		T224	6		T123	22
values[7]	36746	1			T76	11		T224	6		T123	24
values[8]	29292	1			T76	11		T224	6		T123	9
values[9]	25036	1			T76	11		T224	6		T123	9
values[10]	22047	1			T76	11		T224	6		T123	7
values[11]	19897	1			T76	11		T224	6		T123	6
values[12]	18285	1			T76	12		T224	6		T475	2
values[13]	17150	1			T76	11		T224	6		T475	4
values[14]	16143	1			T76	11		T224	6		T475	3
values[15]	15718	1			T76	11		T224	6		T475	1
values[16]	14904	1			T76	11		T224	6		T475	1
values[17]	14276	1			T76	11		T224	6		T475	3
values[18]	13427	1			T76	11		T224	6		T475	3
values[19]	12923	1			T76	11		T224	6		T475	4
values[20]	12644	1			T76	11		T224	6		T475	1
values[21]	12143	1			T76	11		T224	6		T475	3
values[22]	11608	1			T76	11		T224	6		T475	1
values[23]	10866	1			T76	11		T224	6		T475	2
values[24]	10441	1			T76	11		T224	6		T475	1
values[25]	10096	1			T76	11		T224	6		T475	1
values[26]	9519	1			T76	11		T224	6		T475	3
values[27]	9048	1			T76	11		T224	6		T475	5
values[28]	8389	1			T76	11		T224	6		T475	11
values[29]	8091	1			T76	11		T224	6		T475	10
values[30]	7431	1			T76	11		T224	6		T475	5
values[31]	6929	1			T76	11		T224	6		T475	4
values[32]	6593	1			T76	11		T224	6		T475	2
values[33]	6069	1			T76	11		T224	6		T475	1
values[34]	5613	1			T76	11		T224	7		T475	3
values[35]	5239	1			T76	11		T224	6		T475	2
values[36]	4949	1			T76	11		T224	6		T475	4
values[37]	4524	1			T76	11		T224	6		T475	1
values[38]	4425	1			T76	11		T224	6		T475	1
values[39]	4114	1			T76	11		T224	6		T475	1
values[40]	4036	1			T76	11		T224	7		T475	3
values[41]	3744	1			T76	11		T224	6		T475	11
values[42]	3764	1			T76	11		T224	6		T475	7
values[43]	3612	1			T76	11		T224	6		T475	2
values[44]	3456	1			T76	11		T224	6		T475	4
values[45]	3473	1			T76	11		T224	7		T475	2
values[46]	3426	1			T76	11		T224	6		T475	1
values[47]	3409	1			T76	12		T224	6		T475	6
values[48]	3260	1			T76	12		T224	6		T475	7
values[49]	3291	1			T76	11		T224	6		T475	5
values[50]	3295	1			T76	11		T224	6		T475	3
values[51]	3225	1			T76	11		T224	6		T475	1
values[52]	3094	1			T76	11		T224	6		T475	2
values[53]	3081	1			T76	12		T224	6		T475	2
values[54]	2940	1			T76	11		T224	7		T475	1
values[55]	2884	1			T76	11		T224	6		T475	1
values[56]	2821	1			T76	11		T224	6		T475	8
values[57]	2752	1			T76	11		T224	6		T475	7
values[58]	2699	1			T76	13		T224	6		T475	5
values[59]	2704	1			T76	11		T224	6		T475	3
values[60]	2668	1			T76	12		T224	6		T475	4
values[61]	2982	1			T76	12		T224	6		T475	6
values[62]	4227	1			T76	11		T224	6		T475	1
values[63]	18799	1			T76	166		T224	6		T475	8
values[64]	212027	1			T76	2023		T224	1149		T475	54