Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1720678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

22004134

1

T1

32781

T2

59199

T3

7897

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15093929	1			T1	18881		T2	55519		T3	3853
values[0x0]	7246130	1			T1	13900		T2	3680		T3	4044
values[0x1]	1384753	1			T1	1145		T2	15027		T3	634

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	504754	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23220058

1

T1

33926

T2

74226

T3

8531

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10930174	1			T1	16968		T2	37113		T3	4266
valid_sources[0x01]	10928731	1			T1	16958		T2	37113		T3	4265
valid_sources[0x02]	29234	1			T406	4		T132	129		T489	22
valid_sources[0x03]	29251	1			T406	5		T132	239		T489	16
valid_sources[0x04]	29334	1			T54	1		T225	2		T406	20
valid_sources[0x05]	29529	1			T406	48		T132	135		T489	26
valid_sources[0x06]	29376	1			T225	3		T406	13		T132	128
valid_sources[0x07]	29969	1			T54	2		T225	1		T406	8
valid_sources[0x08]	29999	1			T406	18		T132	145		T493	8
valid_sources[0x09]	30139	1			T226	4		T406	11		T132	104
valid_sources[0x0a]	29189	1			T225	1		T406	11		T132	80
valid_sources[0x0b]	29531	1			T406	56		T132	195		T493	6
valid_sources[0x0c]	28778	1			T226	3		T406	53		T132	176
valid_sources[0x0d]	31321	1			T225	1		T406	42		T132	165
valid_sources[0x0e]	29934	1			T77	39		T226	6		T132	147
valid_sources[0x0f]	33649	1			T225	1		T406	10		T132	195
valid_sources[0x10]	29869	1			T406	7		T132	130		T493	12
valid_sources[0x11]	29957	1			T225	3		T406	9		T132	126
valid_sources[0x12]	32771	1			T225	2		T406	22		T132	98
valid_sources[0x13]	30108	1			T225	2		T132	77		T489	16
valid_sources[0x14]	29253	1			T406	54		T132	180		T489	41
valid_sources[0x15]	28641	1			T54	1		T406	25		T132	171
valid_sources[0x16]	31157	1			T225	1		T226	4		T406	17
valid_sources[0x17]	29720	1			T406	11		T132	154		T489	5
valid_sources[0x18]	30325	1			T54	7		T406	9		T132	164
valid_sources[0x19]	29412	1			T225	1		T406	60		T132	189
valid_sources[0x1a]	29179	1			T54	1		T132	165		T489	7
valid_sources[0x1b]	29974	1			T406	23		T132	165		T493	1
valid_sources[0x1c]	29638	1			T225	1		T406	21		T132	166
valid_sources[0x1d]	29454	1			T225	1		T406	16		T132	127
valid_sources[0x1e]	34128	1			T406	10		T132	68		T489	5
valid_sources[0x1f]	28923	1			T225	2		T226	1		T406	43
valid_sources[0x20]	29587	1			T225	1		T406	2		T132	216

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14580742

1

T1

18881

T2

55519

T3

3853

values[0x0]

all_enables

biggest_size

7198213

1

T1

13900

T2

3680

T3

4044

values[0x1]

all_enables

biggest_size

225179

1

T77

22

T54

17

T79

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2794929	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

441805

1

T74

60

T75

22

T76

405

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1095565	1			T74	153		T75	60		T76	879
values[0x0]	1042776	1			T74	148		T75	55		T76	907
values[0x1]	1098393	1			T74	144		T75	59		T76	876

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2164252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1072482

1

T74

142

T75

52

T76

898

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50137	1			T75	4		T76	47		T224	21
valid_sources[0x01]	50054	1			T74	52		T75	4		T76	49
valid_sources[0x02]	51151	1			T75	1		T76	53		T224	16
valid_sources[0x03]	49873	1			T75	2		T76	42		T224	18
valid_sources[0x04]	51154	1			T74	6		T75	4		T76	45
valid_sources[0x05]	51011	1			T74	32		T75	4		T76	43
valid_sources[0x06]	50994	1			T75	2		T76	43		T80	1
valid_sources[0x07]	51071	1			T74	43		T76	35		T224	24
valid_sources[0x08]	51043	1			T75	1		T76	32		T224	31
valid_sources[0x09]	50050	1			T74	6		T75	1		T76	40
valid_sources[0x0a]	50551	1			T75	2		T76	46		T224	29
valid_sources[0x0b]	49187	1			T75	8		T76	46		T224	30
valid_sources[0x0c]	51014	1			T75	2		T76	35		T80	1
valid_sources[0x0d]	51392	1			T74	40		T75	6		T76	41
valid_sources[0x0e]	50703	1			T76	50		T80	1		T224	19
valid_sources[0x0f]	50547	1			T74	19		T75	2		T76	33
valid_sources[0x10]	50953	1			T74	18		T76	39		T80	2
valid_sources[0x11]	50576	1			T74	5		T75	2		T76	38
valid_sources[0x12]	50349	1			T74	5		T75	2		T76	41
valid_sources[0x13]	51005	1			T75	2		T76	40		T224	20
valid_sources[0x14]	50623	1			T75	7		T76	42		T224	26
valid_sources[0x15]	50279	1			T75	1		T76	44		T80	1
valid_sources[0x16]	51125	1			T74	6		T75	3		T76	44
valid_sources[0x17]	50231	1			T75	3		T76	35		T224	21
valid_sources[0x18]	49855	1			T74	19		T75	4		T76	34
valid_sources[0x19]	50029	1			T74	12		T75	3		T76	42
valid_sources[0x1a]	50926	1			T75	2		T76	40		T224	17
valid_sources[0x1b]	51068	1			T75	2		T76	42		T224	21
valid_sources[0x1c]	50424	1			T75	2		T76	41		T224	18
valid_sources[0x1d]	51251	1			T75	2		T76	44		T224	20
valid_sources[0x1e]	49995	1			T74	7		T75	5		T76	43
valid_sources[0x1f]	50814	1			T76	50		T224	23		T123	4
valid_sources[0x20]	50740	1			T74	19		T75	4		T76	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46656

1

T74

3

T75

3

T76

41

values[0x0]

all_enables

biggest_size

348531

1

T74

51

T75

14

T76

329

values[0x1]

all_enables

biggest_size

46618

1

T74

6

T75

5

T76

35

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2982644	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

485420

1

T74

53

T75

33

T76

363

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1188871	1			T74	167		T75	63		T76	870
values[0x0]	1091498	1			T74	131		T75	66		T76	821
values[0x1]	1187695	1			T74	144		T75	49		T76	887

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2288633	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1179431

1

T74

145

T75

73

T76

902

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54226	1			T75	6		T76	39		T80	2
valid_sources[0x01]	53639	1			T74	32		T75	9		T76	42
valid_sources[0x02]	54647	1			T75	1		T76	37		T224	26
valid_sources[0x03]	53983	1			T76	30		T80	1		T224	24
valid_sources[0x04]	53919	1			T74	11		T75	4		T76	34
valid_sources[0x05]	53775	1			T74	16		T75	7		T76	31
valid_sources[0x06]	53454	1			T76	31		T80	1		T224	19
valid_sources[0x07]	54390	1			T74	40		T76	37		T80	1
valid_sources[0x08]	54007	1			T76	47		T80	1		T224	24
valid_sources[0x09]	54676	1			T74	10		T75	2		T76	36
valid_sources[0x0a]	54664	1			T75	7		T76	45		T80	3
valid_sources[0x0b]	54282	1			T76	42		T224	25		T123	2
valid_sources[0x0c]	53796	1			T75	1		T76	39		T224	23
valid_sources[0x0d]	53580	1			T74	43		T76	50		T224	26
valid_sources[0x0e]	55366	1			T76	38		T80	2		T224	21
valid_sources[0x0f]	53870	1			T74	7		T75	9		T76	46
valid_sources[0x10]	54095	1			T74	12		T76	35		T224	18
valid_sources[0x11]	54523	1			T74	14		T76	50		T80	5
valid_sources[0x12]	52617	1			T74	12		T75	1		T76	37
valid_sources[0x13]	54559	1			T75	11		T76	43		T80	3
valid_sources[0x14]	54143	1			T75	3		T76	40		T224	19
valid_sources[0x15]	54141	1			T76	50		T224	29		T123	2
valid_sources[0x16]	52996	1			T74	16		T76	39		T224	28
valid_sources[0x17]	54708	1			T75	4		T76	37		T80	3
valid_sources[0x18]	53919	1			T74	15		T75	2		T76	40
valid_sources[0x19]	53584	1			T74	24		T75	3		T76	46
valid_sources[0x1a]	54354	1			T76	42		T80	2		T224	26
valid_sources[0x1b]	54696	1			T76	37		T80	1		T224	18
valid_sources[0x1c]	54570	1			T76	52		T224	25		T123	4
valid_sources[0x1d]	53952	1			T76	48		T224	28		T123	5
valid_sources[0x1e]	54513	1			T74	18		T75	4		T76	53
valid_sources[0x1f]	55126	1			T75	1		T76	24		T80	4
valid_sources[0x20]	54875	1			T74	14		T76	40		T80	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51432

1

T74

4

T75

4

T76

32

values[0x0]

all_enables

biggest_size

382902

1

T74

45

T75

27

T76

284

values[0x1]

all_enables

biggest_size

51086

1

T74

4

T75

2

T76

47

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2822668	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

445838

1

T74

87

T75

15

T76

365

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1108829	1			T74	176		T75	33		T76	993
values[0x0]	1051566	1			T74	178		T75	45		T76	932
values[0x1]	1108111	1			T74	167		T75	49		T76	955

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2184214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1084292

1

T74

190

T75

33

T76

936

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50655	1			T75	2		T76	52		T224	27
valid_sources[0x01]	50356	1			T74	33		T76	50		T224	23
valid_sources[0x02]	51636	1			T75	2		T76	45		T80	2
valid_sources[0x03]	51158	1			T75	3		T76	57		T224	23
valid_sources[0x04]	51170	1			T74	17		T75	6		T76	56
valid_sources[0x05]	49666	1			T74	19		T75	4		T76	45
valid_sources[0x06]	50323	1			T75	3		T76	42		T224	20
valid_sources[0x07]	50779	1			T74	31		T75	1		T76	36
valid_sources[0x08]	51030	1			T76	52		T224	24		T123	5
valid_sources[0x09]	51280	1			T74	17		T75	2		T76	41
valid_sources[0x0a]	51903	1			T75	1		T76	43		T224	26
valid_sources[0x0b]	51585	1			T76	43		T224	25		T123	4
valid_sources[0x0c]	51360	1			T75	2		T76	44		T224	25
valid_sources[0x0d]	51086	1			T74	34		T76	49		T224	24
valid_sources[0x0e]	51901	1			T75	3		T76	42		T80	2
valid_sources[0x0f]	50228	1			T74	9		T75	2		T76	38
valid_sources[0x10]	51473	1			T74	8		T75	5		T76	51
valid_sources[0x11]	51664	1			T74	17		T75	1		T76	38
valid_sources[0x12]	50929	1			T74	5		T75	4		T76	46
valid_sources[0x13]	51756	1			T75	1		T76	53		T80	2
valid_sources[0x14]	50373	1			T75	1		T76	45		T80	2
valid_sources[0x15]	51525	1			T75	5		T76	43		T224	22
valid_sources[0x16]	50755	1			T74	16		T75	5		T76	52
valid_sources[0x17]	51251	1			T75	2		T76	47		T224	19
valid_sources[0x18]	50367	1			T74	13		T76	39		T224	18
valid_sources[0x19]	51497	1			T74	34		T75	2		T76	41
valid_sources[0x1a]	51817	1			T75	2		T76	36		T224	27
valid_sources[0x1b]	50890	1			T75	1		T76	47		T224	23
valid_sources[0x1c]	50345	1			T75	1		T76	43		T80	1
valid_sources[0x1d]	50592	1			T75	3		T76	59		T80	3
valid_sources[0x1e]	51224	1			T74	20		T75	2		T76	44
valid_sources[0x1f]	51806	1			T75	5		T76	44		T224	29
valid_sources[0x20]	51040	1			T74	18		T76	37		T80	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47043

1

T74

5

T76

39

T224

26

values[0x0]

all_enables

biggest_size

351541

1

T74

70

T75

13

T76

290

values[0x1]

all_enables

biggest_size

47254

1

T74

12

T75

2

T76

36