Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372285798	39820835	0	0
DepthKnown_A	372285798	372187341	0	0
RvalidKnown_A	372285798	372187341	0	0
WreadyKnown_A	372285798	372187341	0	0
gen_passthru_fifo.paramCheckPass	898	898	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	39820835	0	0
T1	821864	387424	0	0
T2	601188	54037	0	0
T3	105317	13023	0	0
T4	115908	141053	0	0
T15	625072	94355	0	0
T31	172470	13557	0	0
T53	671223	98770	0	0
T62	303794	36372	0	0
T87	373413	45794	0	0
T88	145329	23892	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	898	898	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372285798	30506412	0	0
DepthKnown_A	372285798	372187341	0	0
RvalidKnown_A	372285798	372187341	0	0
WreadyKnown_A	372285798	372187341	0	0
gen_passthru_fifo.paramCheckPass	898	898	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	30506412	0	0
T1	821864	198583	0	0
T2	601188	50128	0	0
T3	105317	10189	0	0
T4	115908	94535	0	0
T15	625072	83157	0	0
T31	172470	9266	0	0
T53	671223	87294	0	0
T62	303794	28085	0	0
T87	373413	36138	0	0
T88	145329	16551	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	898	898	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372285798	22225169	0	0
DepthKnown_A	372285798	372187341	0	0
RvalidKnown_A	372285798	372187341	0	0
WreadyKnown_A	372285798	372187341	0	0
gen_passthru_fifo.paramCheckPass	898	898	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	22225169	0	0
T1	821864	37077	0	0
T2	601188	74428	0	0
T3	105317	9114	0	0
T4	115908	67109	0	0
T15	625072	98134	0	0
T31	172470	6899	0	0
T53	671223	77208	0	0
T62	303794	16257	0	0
T87	373413	44511	0	0
T88	145329	8177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	898	898	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	372285798	21881785	0	0
DepthKnown_A	372285798	372187341	0	0
RvalidKnown_A	372285798	372187341	0	0
WreadyKnown_A	372285798	372187341	0	0
gen_passthru_fifo.paramCheckPass	898	898	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	21881785	0	0
T1	821864	33926	0	0
T2	601188	74226	0	0
T3	105317	8531	0	0
T4	115908	65002	0	0
T15	625072	97975	0	0
T31	172470	6657	0	0
T53	671223	76677	0	0
T62	303794	15806	0	0
T87	373413	41904	0	0
T88	145329	7903	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	372187341	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	898	898	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	433144447	88868	0	0
DepthKnown_A	433144447	433034262	0	0
RvalidKnown_A	433144447	433034262	0	0
WreadyKnown_A	433144447	433034262	0	0
gen_passthru_fifo.paramCheckPass	2788	2788	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	88868	0	0
T1	821864	98	0	0
T2	601188	53	0	0
T3	105317	34	0	0
T4	115908	282	0	0
T15	625072	13	0	0
T31	172470	30	0	0
T53	671223	38	0	0
T62	303794	60	0	0
T87	373413	14	0	0
T88	145329	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2788	2788	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	433144447	90997	0	0
DepthKnown_A	433144447	433034262	0	0
RvalidKnown_A	433144447	433034262	0	0
WreadyKnown_A	433144447	433034262	0	0
gen_passthru_fifo.paramCheckPass	2788	2788	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	90997	0	0
T1	821864	98	0	0
T2	601188	53	0	0
T3	105317	34	0	0
T4	115908	282	0	0
T15	625072	13	0	0
T31	172470	30	0	0
T53	671223	38	0	0
T62	303794	60	0	0
T87	373413	14	0	0
T88	145329	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2788	2788	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	433144447	49069	0	0
DepthKnown_A	433144447	433034262	0	0
RvalidKnown_A	433144447	433034262	0	0
WreadyKnown_A	433144447	433034262	0	0
gen_passthru_fifo.paramCheckPass	2788	2788	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	49069	0	0
T1	821864	98	0	0
T2	601188	52	0	0
T3	105317	33	0	0
T4	115908	246	0	0
T15	625072	12	0	0
T31	172470	28	0	0
T53	671223	32	0	0
T62	303794	57	0	0
T87	373413	13	0	0
T88	145329	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2788	2788	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	433144447	49069	0	0
DepthKnown_A	433144447	433034262	0	0
RvalidKnown_A	433144447	433034262	0	0
WreadyKnown_A	433144447	433034262	0	0
gen_passthru_fifo.paramCheckPass	2788	2788	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	49069	0	0
T1	821864	98	0	0
T2	601188	52	0	0
T3	105317	33	0	0
T4	115908	246	0	0
T15	625072	12	0	0
T31	172470	28	0	0
T53	671223	32	0	0
T62	303794	57	0	0
T87	373413	13	0	0
T88	145329	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2788	2788	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	433144447	39799	0	0
DepthKnown_A	433144447	433034262	0	0
RvalidKnown_A	433144447	433034262	0	0
WreadyKnown_A	433144447	433034262	0	0
gen_passthru_fifo.paramCheckPass	2788	2788	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	39799	0	0
T2	601188	1	0	0
T3	105317	1	0	0
T4	115908	36	0	0
T15	625072	1	0	0
T31	172470	2	0	0
T53	671223	6	0	0
T59	229464	54	0	0
T62	303794	3	0	0
T87	373413	1	0	0
T88	145329	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2788	2788	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	433144447	41928	0	0
DepthKnown_A	433144447	433034262	0	0
RvalidKnown_A	433144447	433034262	0	0
WreadyKnown_A	433144447	433034262	0	0
gen_passthru_fifo.paramCheckPass	2788	2788	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	41928	0	0
T2	601188	1	0	0
T3	105317	1	0	0
T4	115908	36	0	0
T15	625072	1	0	0
T31	172470	2	0	0
T53	671223	6	0	0
T59	229464	54	0	0
T62	303794	3	0	0
T87	373413	1	0	0
T88	145329	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433144447	433034262	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2788	2788	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0