Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sysrst_ctrl_aon 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_sysrst_ctrl_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : sysrst_ctrl
TotalCoveredPercent
Totals 50 50 100.00
Total Bits 334 334 100.00
Total Bits 0->1 167 167 100.00
Total Bits 1->0 167 167 100.00

Ports 50 50 100.00
Port Bits 334 334 100.00
Port Bits 0->1 167 167 100.00
Port Bits 1->0 167 167 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T31,T4 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T1,T31,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T62,T44,T391 Yes T62,T44,T391 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T62,T44,T391 Yes T62,T44,T391 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[7:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
tl_i.a_address[15:8] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[21:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T77,*T78,*T54 Yes T77,T78,T54 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T54,T79 Yes T77,T54,T79 INPUT
tl_i.a_valid Yes Yes T62,T44,T391 Yes T62,T44,T391 INPUT
tl_o.a_ready Yes Yes T62,T44,T391 Yes T62,T44,T391 OUTPUT
tl_o.d_error Yes Yes T74,T75,T80 Yes T74,T80,T224 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T62,T391,T102 Yes T62,T391,T102 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T62,T44,T391 Yes T62,T44,T391 OUTPUT
tl_o.d_data[31:0] Yes Yes T62,T44,T391 Yes T62,T44,T391 OUTPUT
tl_o.d_sink Yes Yes T74,T75,T80 Yes T74,T80,T122 OUTPUT
tl_o.d_source[5:0] Yes Yes *T74,*T80,*T224 Yes T74,T75,T80 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T74,T80,T122 Yes T74,T75,T80 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T62,*T391,*T102 Yes T62,T44,T391 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T62,T44,T391 Yes T62,T44,T391 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T272,T151,T83 Yes T272,T151,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T151,T83,T84 Yes T151,T83,T84 INPUT
alert_rx_i[0].ping_p Yes Yes T151,T83,T84 Yes T151,T83,T84 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T272,T151,T83 Yes T272,T151,T83 OUTPUT
wkup_req_o Yes Yes T62,T391,T102 Yes T62,T391,T102 OUTPUT
rst_req_o Yes Yes T62,T391,T102 Yes T62,T391,T102 OUTPUT
intr_event_detected_o Yes Yes T177,T275,T288 Yes T177,T275,T288 OUTPUT
cio_ac_present_i Yes Yes T177,T19,T178 Yes T177,T19,T178 INPUT
cio_ec_rst_l_i Yes Yes T6,T177,T19 Yes T6,T177,T19 INPUT
cio_key0_in_i Yes Yes T62,T391,T102 Yes T62,T391,T102 INPUT
cio_key1_in_i Yes Yes T177,T19,T20 Yes T177,T19,T20 INPUT
cio_key2_in_i Yes Yes T177,T19,T178 Yes T177,T19,T178 INPUT
cio_pwrb_in_i Yes Yes T16,T177,T19 Yes T16,T177,T19 INPUT
cio_lid_open_i Yes Yes T19,T178,T35 Yes T19,T178,T35 INPUT
cio_flash_wp_l_i Yes Yes T177,T19,T20 Yes T6,T177,T19 INPUT
cio_bat_disable_o Yes Yes T62,T391,T102 Yes T62,T391,T102 OUTPUT
cio_flash_wp_l_o Yes Yes T19,T20,T21 Yes T19,T20,T35 OUTPUT
cio_ec_rst_l_o Yes Yes T19,T20,T21 Yes T19,T20,T21 OUTPUT
cio_key0_out_o Yes Yes T62,T391,T102 Yes T62,T391,T102 OUTPUT
cio_key1_out_o Yes Yes T177,T19,T20 Yes T177,T19,T20 OUTPUT
cio_key2_out_o Yes Yes T177,T19,T178 Yes T177,T19,T20 OUTPUT
cio_pwrb_out_o Yes Yes T16,T177,T19 Yes T16,T177,T19 OUTPUT
cio_z3_wakeup_o Yes Yes T19,T21,T642 Yes T19,T20,T35 OUTPUT
cio_bat_disable_en_o Unreachable Unreachable Unreachable OUTPUT
cio_flash_wp_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_ec_rst_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key0_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key1_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key2_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pwrb_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_z3_wakeup_en_o Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%