Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_uart0 100.00 100.00
tb.dut.top_earlgrey.u_uart1 100.00 100.00
tb.dut.top_earlgrey.u_uart2 100.00 100.00
tb.dut.top_earlgrey.u_uart3 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : uart
TotalCoveredPercent
Totals 39 39 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 39 39 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T31,T53 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T2,T179,T180 Yes T2,T179,T180 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T2,T179,T180 Yes T2,T179,T180 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T77,*T78,*T54 Yes T77,T78,T54 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T54,T79 Yes T77,T54,T79 INPUT
tl_i.a_valid Yes Yes T2,T179,T180 Yes T2,T179,T180 INPUT
tl_o.a_ready Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
tl_o.d_error Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
tl_o.d_sink Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
tl_o.d_source[5:0] Yes Yes *T56,*T74,*T76 Yes T56,T74,T75 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T2,*T179,*T180 Yes T2,T179,T180 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T307,T616,T313 Yes T307,T616,T313 INPUT
alert_rx_i[0].ping_n Yes Yes T151,T83,T84 Yes T151,T83,T84 INPUT
alert_rx_i[0].ping_p Yes Yes T151,T83,T84 Yes T151,T83,T84 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T307,T616,T313 Yes T307,T616,T313 OUTPUT
cio_rx_i Yes Yes T1,T2,T31 Yes T1,T2,T3 INPUT
cio_tx_o Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
intr_rx_watermark_o Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
intr_tx_empty_o Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
intr_rx_overflow_o Yes Yes T2,T179,T180 Yes T2,T179,T180 OUTPUT
intr_rx_frame_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_break_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_timeout_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_parity_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0
TotalCoveredPercent
Totals 39 39 100.00
Total Bits 302 302 100.00
Total Bits 0->1 151 151 100.00
Total Bits 1->0 151 151 100.00

Ports 39 39 100.00
Port Bits 302 302 100.00
Port Bits 0->1 151 151 100.00
Port Bits 1->0 151 151 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T31,T53 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T141,T275,T187 Yes T141,T275,T187 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T141,T275,T187 Yes T141,T275,T187 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
tl_i.a_address[29:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T77,*T78,*T54 Yes T77,T78,T54 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T54,T79 Yes T77,T54,T79 INPUT
tl_i.a_valid Yes Yes T141,T275,T187 Yes T141,T275,T187 INPUT
tl_o.a_ready Yes Yes T141,T275,T187 Yes T141,T275,T187 OUTPUT
tl_o.d_error Yes Yes T74,T75,T80 Yes T74,T75,T80 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T141,T275,T187 Yes T141,T275,T187 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T141,T275,T187 Yes T141,T275,T187 OUTPUT
tl_o.d_data[31:0] Yes Yes T141,T275,T187 Yes T141,T275,T187 OUTPUT
tl_o.d_sink Yes Yes T74,T75,T76 Yes T74,T75,T80 OUTPUT
tl_o.d_source[5:0] Yes Yes *T56,*T74,*T76 Yes T56,T74,T75 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T80 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T141,*T275,*T187 Yes T141,T275,T187 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T141,T275,T187 Yes T141,T275,T187 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T84,T219 Yes T83,T84,T219 INPUT
alert_rx_i[0].ping_n Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T84,T219 Yes T83,T84,T219 OUTPUT
cio_rx_i Yes Yes T1,T31,T4 Yes T1,T2,T3 INPUT
cio_tx_o Yes Yes T141,T187,T188 Yes T141,T187,T188 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T141,T275,T187 Yes T141,T275,T187 OUTPUT
intr_rx_watermark_o Yes Yes T141,T275,T187 Yes T141,T275,T187 OUTPUT
intr_tx_empty_o Yes Yes T141,T275,T187 Yes T141,T275,T187 OUTPUT
intr_rx_overflow_o Yes Yes T141,T275,T187 Yes T141,T275,T187 OUTPUT
intr_rx_frame_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_break_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_timeout_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_parity_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1
TotalCoveredPercent
Totals 39 39 100.00
Total Bits 304 304 100.00
Total Bits 0->1 152 152 100.00
Total Bits 1->0 152 152 100.00

Ports 39 39 100.00
Port Bits 304 304 100.00
Port Bits 0->1 152 152 100.00
Port Bits 1->0 152 152 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T31,T53 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T179,T180,T181 Yes T179,T180,T181 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T179,T180,T181 Yes T179,T180,T181 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T77,*T78,*T54 Yes T77,T78,T54 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T54,T79 Yes T77,T54,T79 INPUT
tl_i.a_valid Yes Yes T179,T180,T181 Yes T179,T180,T181 INPUT
tl_o.a_ready Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
tl_o.d_error Yes Yes T74,T75,T80 Yes T74,T75,T80 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
tl_o.d_data[31:0] Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
tl_o.d_sink Yes Yes T74,T75,T80 Yes T74,T75,T80 OUTPUT
tl_o.d_source[5:0] Yes Yes *T56,*T74,*T80 Yes T56,T74,T75 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T74,T75,T80 Yes T74,T75,T80 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T179,*T180,*T181 Yes T179,T180,T181 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T307,T151,T83 Yes T307,T151,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T151,T83,T84 Yes T151,T83,T84 INPUT
alert_rx_i[0].ping_p Yes Yes T151,T83,T84 Yes T151,T83,T84 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T307,T151,T83 Yes T307,T151,T83 OUTPUT
cio_rx_i Yes Yes T179,T180,T181 Yes T179,T180,T181 INPUT
cio_tx_o Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
intr_rx_watermark_o Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
intr_tx_empty_o Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
intr_rx_overflow_o Yes Yes T179,T180,T181 Yes T179,T180,T181 OUTPUT
intr_rx_frame_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_break_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_timeout_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_parity_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2
TotalCoveredPercent
Totals 39 39 100.00
Total Bits 304 304 100.00
Total Bits 0->1 152 152 100.00
Total Bits 1->0 152 152 100.00

Ports 39 39 100.00
Port Bits 304 304 100.00
Port Bits 0->1 152 152 100.00
Port Bits 1->0 152 152 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T31,T53 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T2,T116,T264 Yes T2,T116,T264 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T2,T116,T264 Yes T2,T116,T264 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T77,*T78,*T54 Yes T77,T78,T54 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T54,T79 Yes T77,T54,T79 INPUT
tl_i.a_valid Yes Yes T2,T116,T264 Yes T2,T116,T264 INPUT
tl_o.a_ready Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
tl_o.d_error Yes Yes T74,T75,T76 Yes T74,T76,T122 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
tl_o.d_data[31:0] Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
tl_o.d_sink Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
tl_o.d_source[5:0] Yes Yes *T56,*T74,*T76 Yes T56,T74,T75 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T2,*T116,*T264 Yes T2,T116,T264 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T313,T83,T368 Yes T313,T83,T368 INPUT
alert_rx_i[0].ping_n Yes Yes T83,T84,T149 Yes T83,T84,T149 INPUT
alert_rx_i[0].ping_p Yes Yes T83,T84,T149 Yes T83,T84,T149 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T313,T83,T368 Yes T313,T83,T368 OUTPUT
cio_rx_i Yes Yes T2,T116,T264 Yes T2,T116,T264 INPUT
cio_tx_o Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
intr_rx_watermark_o Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
intr_tx_empty_o Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
intr_rx_overflow_o Yes Yes T2,T116,T264 Yes T2,T116,T264 OUTPUT
intr_rx_frame_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_break_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_timeout_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_parity_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3
TotalCoveredPercent
Totals 39 39 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 39 39 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T31,T53 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T14,T275,T290 Yes T14,T275,T290 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T14,T275,T290 Yes T14,T275,T290 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T74,*T75,*T76 Yes T74,T75,T76 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T77,*T78,*T54 Yes T77,T78,T54 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T54,T79 Yes T77,T54,T79 INPUT
tl_i.a_valid Yes Yes T14,T275,T290 Yes T14,T275,T290 INPUT
tl_o.a_ready Yes Yes T14,T275,T290 Yes T14,T275,T290 OUTPUT
tl_o.d_error Yes Yes T74,T75,T80 Yes T74,T75,T80 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T14,T275,T290 Yes T14,T275,T290 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T14,T275,T290 Yes T14,T275,T290 OUTPUT
tl_o.d_data[31:0] Yes Yes T14,T275,T290 Yes T14,T275,T290 OUTPUT
tl_o.d_sink Yes Yes T74,T80,T224 Yes T74,T76,T80 OUTPUT
tl_o.d_source[5:0] Yes Yes *T56,*T74,*T80 Yes T56,T74,T75 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T74,T75,T80 Yes T74,T75,T76 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T14,*T275,*T290 Yes T14,T275,T290 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T14,T275,T290 Yes T14,T275,T290 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T616,T83,T617 Yes T616,T83,T617 INPUT
alert_rx_i[0].ping_n Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
alert_rx_i[0].ping_p Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T616,T83,T617 Yes T616,T83,T617 OUTPUT
cio_rx_i Yes Yes T14,T290,T309 Yes T14,T290,T309 INPUT
cio_tx_o Yes Yes T14,T290,T309 Yes T14,T290,T309 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T14,T275,T290 Yes T14,T275,T290 OUTPUT
intr_rx_watermark_o Yes Yes T14,T275,T290 Yes T14,T275,T290 OUTPUT
intr_tx_empty_o Yes Yes T14,T275,T290 Yes T14,T275,T290 OUTPUT
intr_rx_overflow_o Yes Yes T14,T275,T290 Yes T14,T275,T290 OUTPUT
intr_rx_frame_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_break_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_timeout_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT
intr_rx_parity_err_o Yes Yes T275,T288,T298 Yes T275,T288,T298 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%