Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T75,T76,T80	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T75,T80,T224	Yes	T75,T80,T224	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T165,T191,T192	Yes	T165,T191,T192	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T165,T191,T192	Yes	T165,T191,T192	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T225,T226,T75	Yes	T225,T226,T75	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T225,T226,T74	Yes	T225,T226,T74	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T60,T165,T61	Yes	T60,T165,T61	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T31,T53,T4	Yes	T2,T3,T31	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T66,T63,T67	Yes	T66,T63,T67	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T31,T53,T4	Yes	T2,T3,T31	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T31,T53,T4	Yes	T2,T3,T31	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T66,T63,T67	Yes	T66,T63,T67	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T31,T53,T4	Yes	T2,T3,T31	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T66,T63,T67	Yes	T66,T63,T67	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T66,T63,T67	Yes	T66,T63,T67	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T66,T63,T67	Yes	T66,T63,T67	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T66,T63,T67	Yes	T66,T63,T67	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T66,*T63,*T67	Yes	T66,T63,T67	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T66,T63,T67	Yes	T66,T63,T67	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T75,T76,T80	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T233,*T234,*T235	Yes	T233,T234,T235	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T2,T3,T31	Yes	T31,T53,T4	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T31	Yes	T31,T53,T4	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T233,*T234,*T235	Yes	T233,T234,T235	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T31	Yes	T31,T53,T4	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T1,T5,T205	Yes	T1,T5,T205	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T55,T57,T221	Yes	T55,T57,T221	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T110,T396,T397	Yes	T110,T396,T397	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T110,T396,T397	Yes	T110,T396,T397	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T55,T57,T221	Yes	T55,T57,T221	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T110,T396,T397	Yes	T110,T396,T397	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T74,*T75,*T80	Yes	T74,T75,T80	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T110,T396,T397	Yes	T110,T396,T397	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T110,T396,T397	Yes	T110,T396,T397	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T110,T396,T397	Yes	T110,T396,T397	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T75,T80	Yes	T55,T57,T221	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T110,T396,T397	Yes	T110,T396,T397	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T110,*T249,*T398	Yes	T110,T396,T397	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T110,T396,T397	Yes	T110,T396,T397	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T59,T306,T97	Yes	T59,T306,T97	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T74,*T80,*T122	Yes	T74,T80,T122	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T11,T190	Yes	T10,T11,T190	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T76	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T80	Yes	T74,T76,T80	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T146,*T9,*T10	Yes	T146,T9,T10	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T146,T9,T10	Yes	T146,T9,T10	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T74,*T75,*T80	Yes	T74,T75,T80	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T74,*T80,*T122	Yes	T74,T75,T80	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T146,*T33,*T34	Yes	T146,T33,T34	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T146,T33,T34	Yes	T146,T33,T34	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T56,*T74,*T75	Yes	T56,T74,T75	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_usbdev_i.d_error	Yes	Yes	T74,T80,T122	Yes	T74,T76,T80	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T15,T275,T288	Yes	T15,T275,T288	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T275,T288	Yes	T15,T275,T288	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T15,T16,T17	Yes	T15,T17,T18	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T56,*T74,*T76	Yes	T56,T74,T80	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T74,T76,T80	Yes	T74,T80,T122	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T15,*T16,*T17	Yes	T15,T17,T18	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T54,*T74,*T76	Yes	T54,T74,T76	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T74,T76,T80	Yes	T74,T76,T80	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T53	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T31,T53	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T76	Yes	T54,T74,T76	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T54,T74,T75	Yes	T54,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T54,T75,T76	Yes	T54,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T54,T74,T80	Yes	T54,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T74,T80,T122	Yes	T74,T75,T80	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T54,T74,T80	Yes	T54,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T54,*T74,*T80	Yes	T54,T74,T80	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T53	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T317,T318,T631	Yes	T317,T318,T631	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T317,T318,T631	Yes	T317,T318,T631	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T31,T317,T318	Yes	T31,T317,T318	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T317,T318,T631	Yes	T317,T318,T631	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T31,T317,T318	Yes	T31,T317,T318	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T54,*T74,*T75	Yes	T54,T74,T75	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T74,T80,T224	Yes	T74,T80,T224	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T317,T318,T631	Yes	T317,T318,T631	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T31,T317,T318	Yes	T31,T317,T318	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T31,T317,T318	Yes	T31,T317,T318	INPUT
tl_hmac_i.d_error	Yes	Yes	T74,T80,T224	Yes	T74,T80,T224	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T31,T317,T318	Yes	T31,T317,T318	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T317,T318	Yes	T31,T317,T318	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T317,T318,T631	Yes	T317,T318,T631	INPUT
tl_hmac_i.d_sink	Yes	Yes	T74,T80,T224	Yes	T74,T80,T224	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T80	Yes	T54,T74,T75	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T74,T80,T224	Yes	T74,T80,T224	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T317,*T318,*T631	Yes	T317,T318,T631	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T31,T317,T318	Yes	T31,T317,T318	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T3,T31	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T3,T401,T121	Yes	T3,T401,T121	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T31,T401	Yes	T3,T31,T401	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T3,T31,T401	Yes	T3,T31,T401	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T3,T401,T393	Yes	T3,T401,T393	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T3,T31,T401	Yes	T3,T31,T401	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T54,*T56,*T74	Yes	T54,T56,T74	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T3,T401,T393	Yes	T3,T401,T393	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T3,T31,T401	Yes	T3,T31,T401	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T3,T31,T401	Yes	T3,T31,T401	INPUT
tl_kmac_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T3,T31,T401	Yes	T3,T31,T401	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T31,T401	Yes	T3,T31,T401	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T3,T401,T121	Yes	T3,T401,T393	INPUT
tl_kmac_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T54,*T56,*T74	Yes	T54,T56,T74	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T3,*T401,*T121	Yes	T3,T401,T393	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T3,T31,T401	Yes	T3,T31,T401	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T266,T629,T144	Yes	T266,T629,T144	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T266,T629,T144	Yes	T266,T629,T144	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T31,T266,T629	Yes	T31,T266,T629	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T266,T629,T144	Yes	T266,T629,T144	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T31,T266,T629	Yes	T31,T266,T629	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T79,*T74,*T75	Yes	T79,T74,T75	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T31,T266,T629	Yes	T31,T266,T629	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T31,T266,T629	Yes	T31,T266,T629	INPUT
tl_aes_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T31,T266,T629	Yes	T31,T266,T629	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T266,T629,T144	Yes	T266,T629,T144	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T31,T266,T629	Yes	T31,T266,T629	INPUT
tl_aes_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T79,*T74,*T75	Yes	T79,T74,T75	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T74,T80,T123	Yes	T74,T75,T80	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T31,*T266,*T629	Yes	T31,T266,T629	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T31,T266,T629	Yes	T31,T266,T629	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T54,*T74,*T75	Yes	T54,T74,T75	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T80	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T75	Yes	T54,T74,T75	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T53,*T112,*T121	Yes	T53,T112,T121	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T54,*T79,*T74	Yes	T54,T79,T74	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T54,*T79,*T74	Yes	T54,T79,T74	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T53,*T112,*T121	Yes	T53,T112,T121	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T54,*T74,*T75	Yes	T54,T74,T75	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T80	Yes	T54,T74,T75	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T53,*T112,*T121	Yes	T53,T112,T121	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T54,*T74,*T75	Yes	T54,T74,T75	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	INPUT
tl_edn1_i.d_error	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	INPUT
tl_edn1_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T80,T122	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T80	Yes	T54,T74,T75	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T53,*T112,*T121	Yes	T53,T112,T121	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T53,T112,T121	Yes	T53,T112,T121	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T74,*T75,*T80	Yes	T74,T75,T80	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T80,T224	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T59	Yes	T2,T4,T59	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T76	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T74,*T80,*T123	Yes	T74,T75,T80	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T80,T224	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T53,*T4	Yes	T2,T53,T4	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T53,T4	Yes	T2,T53,T4	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T100,T111,T114	Yes	T100,T111,T114	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T100,T111	Yes	T31,T100,T111	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T31,T100,T111	Yes	T31,T100,T111	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T100,T111,T114	Yes	T100,T111,T114	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T31,T100,T111	Yes	T31,T100,T111	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T77,*T54,*T225	Yes	T77,T54,T225	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T31,T100,T111	Yes	T31,T100,T111	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T31,T100,T111	Yes	T31,T100,T111	INPUT
tl_otbn_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T100,T111,T114	Yes	T100,T111,T114	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T100,T111,T114	Yes	T100,T111,T114	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T100,T111,T114	Yes	T100,T111,T114	INPUT
tl_otbn_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T77,*T54,*T225	Yes	T77,T54,T225	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T100,*T111,*T114	Yes	T100,T111,T114	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T100,T111,T114	Yes	T100,T111,T114	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T121,T44,T111	Yes	T121,T44,T111	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T121,T44,T111	Yes	T121,T44,T111	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T121,T44,T111	Yes	T121,T44,T111	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T121,T111,T193	Yes	T121,T111,T193	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T121,T44,T111	Yes	T121,T44,T111	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T54,*T74,*T75	Yes	T54,T74,T75	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T121,T44,T111	Yes	T121,T44,T111	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T121,T44,T111	Yes	T121,T44,T111	INPUT
tl_keymgr_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T121,T111,T193	Yes	T121,T111,T193	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T121,T44,T111	Yes	T121,T44,T111	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T121,T44,T111	Yes	T121,T44,T111	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T74,T80,T122	Yes	T74,T75,T80	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T80	Yes	T54,T74,T75	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T121,*T111,*T193	Yes	T121,T44,T111	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T121,T44,T111	Yes	T121,T44,T111	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T31	Yes	T2,T3,T31	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T165,T160,T161	Yes	T165,T160,T161	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T165,T215,T399	Yes	T165,T215,T399	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T165,T215,T399	Yes	T165,T215,T399	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T165,T160,T161	Yes	T165,T160,T161	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T165,T215,T399	Yes	T165,T215,T399	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T74,*T75,*T80	Yes	T74,T75,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T165,T215,T399	Yes	T165,T215,T399	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T165,T215,T399	Yes	T165,T215,T399	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T165,T273,T274	Yes	T165,T273,T274	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T165,T160,T161	Yes	T165,T160,T161	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T165,T160,T161	Yes	T165,T160,T161	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T74,*T76,*T80	Yes	T74,T75,T80	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T165,*T160,*T161	Yes	T165,T215,T399	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T165,T215,T399	Yes	T165,T215,T399	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T53	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range