Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_pad_wrapper
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[23].u_dio_pad.gen_generic.u_impl_generic

Line Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 )
Line Coverage for Module self-instances :
SCORE
tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[23].u_dio_pad.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3900
CONT_ASSIGN5300
CONT_ASSIGN6011100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
53 unreachable
60 1 1
62 1 1
67 1 1


Line Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Line Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic

SCORELINE
100.00 100.00
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3900
CONT_ASSIGN9800
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
98 unreachable
103 1 1
104 1 1


Cond Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 )
Cond Coverage for Module self-instances :
SCORE
tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[23].u_dio_pad.gen_generic.u_impl_generic

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       62
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       67
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

SCORECOND
100.00 100.00
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT35,T36,T37
11CoveredT15,T6,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT35,T36,T37
01CoveredT1,T2,T3
10CoveredT35,T36,T37

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT35,T36,T37
11CoveredT35,T36,T37

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T6,T22

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T9,T10
11CoveredT15,T6,T22

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T9,T10

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T6,T22
11CoveredT6,T9,T10

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T9,T10

Branch Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 )
Branch Coverage for Module self-instances :
SCORE
tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[23].u_dio_pad.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 60 1 1 100.00
TERNARY 67 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 67 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic

SCORE
tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

SCOREBRANCH
100.00 100.00
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T15,T6,T22
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T6,T9,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T38,T9,T10
0 Covered T1,T2,T3


Assert Coverage for Module : prim_generic_pad_wrapper
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 63758 63758 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63758 63758 0 0
T1 71 71 0 0
T2 71 71 0 0
T3 71 71 0 0
T4 71 71 0 0
T15 71 71 0 0
T31 71 71 0 0
T53 71 71 0 0
T62 71 71 0 0
T87 71 71 0 0
T88 71 71 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%