Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T59,T306,T97	Yes	T59,T306,T97	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T141,T275,T187	Yes	T141,T275,T187	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T141,T275,T187	Yes	T141,T275,T187	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T141,T275,T187	Yes	T141,T275,T187	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T141,T275,T187	Yes	T141,T275,T187	INPUT
tl_uart0_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T141,T275,T187	Yes	T141,T275,T187	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T141,T275,T187	Yes	T141,T275,T187	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T141,T275,T187	Yes	T141,T275,T187	INPUT
tl_uart0_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T80	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T56,*T74,*T76	Yes	T56,T74,T75	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T80	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T141,*T275,*T187	Yes	T141,T275,T187	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T141,T275,T187	Yes	T141,T275,T187	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	INPUT
tl_uart1_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	INPUT
tl_uart1_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T56,*T74,*T80	Yes	T56,T74,T75	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T179,*T180,*T181	Yes	T179,T180,T181	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T179,T180,T181	Yes	T179,T180,T181	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T2,T116,T264	Yes	T2,T116,T264	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T2,T116,T264	Yes	T2,T116,T264	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T2,T116,T264	Yes	T2,T116,T264	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T2,T116,T264	Yes	T2,T116,T264	INPUT
tl_uart2_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T76,T122	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T2,T116,T264	Yes	T2,T116,T264	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T116,T264	Yes	T2,T116,T264	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T2,T116,T264	Yes	T2,T116,T264	INPUT
tl_uart2_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T56,*T74,*T76	Yes	T56,T74,T75	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T2,*T116,*T264	Yes	T2,T116,T264	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T2,T116,T264	Yes	T2,T116,T264	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T14,T275,T290	Yes	T14,T275,T290	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T14,T275,T290	Yes	T14,T275,T290	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T14,T275,T290	Yes	T14,T275,T290	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T14,T275,T290	Yes	T14,T275,T290	INPUT
tl_uart3_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T14,T275,T290	Yes	T14,T275,T290	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T14,T275,T290	Yes	T14,T275,T290	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T14,T275,T290	Yes	T14,T275,T290	INPUT
tl_uart3_i.d_sink	Yes	Yes	T74,T80,T224	Yes	T74,T76,T80	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T56,*T74,*T80	Yes	T56,T74,T75	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T76	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T14,*T275,*T290	Yes	T14,T275,T290	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T14,T275,T290	Yes	T14,T275,T290	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T287,T345,T54	Yes	T287,T345,T54	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T287,T345,T54	Yes	T287,T345,T54	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c0_i.d_error	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T287,T54,T301	Yes	T287,T54,T301	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T80	Yes	T54,T74,T75	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T74,T80,T122	Yes	T74,T75,T80	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T287,*T345,*T54	Yes	T287,T345,T54	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T287,T296,T345	Yes	T287,T296,T345	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T287,T296,T345	Yes	T287,T296,T345	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c1_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T287,T296,T54	Yes	T287,T296,T54	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T76	Yes	T54,T74,T75	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T287,*T296,*T345	Yes	T287,T296,T345	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T287,T345,T54	Yes	T287,T345,T54	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T287,T345,T54	Yes	T287,T345,T54	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c2_i.d_error	Yes	Yes	T74,T76,T80	Yes	T74,T75,T76	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T287,T54,T302	Yes	T287,T54,T302	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T74,T76,T80	Yes	T74,T76,T80	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T76	Yes	T54,T74,T75	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T76,T80	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T287,*T345,*T54	Yes	T287,T345,T54	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T287,T219,T220	Yes	T287,T219,T220	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T184,T146,T182	Yes	T184,T146,T182	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T184,T146,T182	Yes	T184,T146,T182	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T184,T146,T182	Yes	T184,T146,T182	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T184,T146,T182	Yes	T184,T146,T182	INPUT
tl_pattgen_i.d_error	Yes	Yes	T74,T75,T122	Yes	T74,T75,T80	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T184,T146,T182	Yes	T184,T146,T182	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T184,T146,T182	Yes	T184,T146,T182	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T184,T146,T182	Yes	T184,T146,T182	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T54,*T56,T74	Yes	T54,T56,T74	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T123	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T184,*T146,*T182	Yes	T184,T146,T182	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T184,T146,T182	Yes	T184,T146,T182	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T183,T609,T630	Yes	T183,T609,T630	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T183,T609,T630	Yes	T183,T609,T630	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T183,T609,T630	Yes	T183,T609,T630	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T183,T609,T630	Yes	T183,T609,T630	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T74,T80,T123	Yes	T74,T80,T122	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T183,T609,T630	Yes	T183,T609,T630	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T183,T609,T630	Yes	T183,T609,T630	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T183,T609,T630	Yes	T183,T609,T630	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	T74,*T80,*T122	Yes	T74,T75,T80	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T183,*T609,*T630	Yes	T183,T609,T630	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T183,T609,T630	Yes	T183,T609,T630	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	INPUT
tl_gpio_i.d_error	Yes	Yes	T74,T76,T80	Yes	T74,T75,T76	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T13,T287,T86	Yes	T13,T287,T86	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T287,T86	Yes	T12,T13,T287	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T13,T287,T86	Yes	T12,T13,T287	INPUT
tl_gpio_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T76	Yes	T54,T74,T76	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T76,T80	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T31,*T53,*T4	Yes	T2,T3,T31	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T140,T38,T141	Yes	T140,T38,T141	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T140,T38,T141	Yes	T140,T38,T141	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T140,T38,T141	Yes	T140,T38,T141	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T140,T38,T141	Yes	T140,T38,T141	INPUT
tl_spi_device_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T76,T80	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T140,T38,T141	Yes	T140,T38,T141	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T38,T141	Yes	T140,T38,T141	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T140,T38,T141	Yes	T140,T38,T141	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T74,*T76,*T80	Yes	T74,T75,T76	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T140,*T38,*T141	Yes	T140,T38,T141	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T140,T38,T141	Yes	T140,T38,T141	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T230,T231,T146	Yes	T230,T231,T146	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T230,T231,T146	Yes	T230,T231,T146	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T230,T231,T146	Yes	T230,T231,T146	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T230,T231,T146	Yes	T230,T231,T146	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T76	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T230,T231,T146	Yes	T230,T231,T146	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T230,T231,T146	Yes	T230,T231,T146	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T230,T231,T645	Yes	T230,T231,T146	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T74,*T76,*T80	Yes	T74,T75,T80	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T230,*T231,*T146	Yes	T230,T231,T146	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T230,T231,T146	Yes	T230,T231,T146	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T31,T53,T4	Yes	T31,T53,T4	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T31,T53,T4	Yes	T31,T53,T4	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T31,T53,T4	Yes	T31,T53,T4	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T31,T53,T4	Yes	T31,T53,T4	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T75,T76,T122	Yes	T75,T76,T80	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T31,T53,T4	Yes	T31,T53,T4	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T53,T4	Yes	T31,T53,T4	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T31,T53,T4	Yes	T31,T53,T4	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T31,*T53,*T4	Yes	T31,T53,T4	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T31,T53,T4	Yes	T31,T53,T4	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T53,T4	Yes	T2,T3,T31	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T31,T53,T4	Yes	T2,T3,T31	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T76	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T74,*T80,*T224	Yes	T74,T75,T80	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T80	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T31	Yes	T2,T3,T31	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T31,T179	Yes	T2,T31,T179	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T31,T53	Yes	T2,T31,T53	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T179,T180	Yes	T2,T179,T180	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T79,*T74,*T80	Yes	T79,T74,T75	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T31,*T179	Yes	T2,T31,T179	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T54,*T56,*T74	Yes	T54,T56,T74	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T74,T80,T122	Yes	T74,T80,T122	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T78,*T54,*T145	Yes	T78,T54,T145	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T121,*T41,*T140	Yes	T121,T41,T140	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T54,T56,T74	Yes	T54,T56,T74	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T54,T56,T74	Yes	T54,T56,T74	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T54,T56,T74	Yes	T54,T56,T74	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T2,T3,T31	Yes	T31,T53,T4	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T54,T56,T74	Yes	T54,T56,T74	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T56,T74	Yes	T54,T56,T74	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T2,T3,T31	Yes	T31,T53,T4	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T54,*T56,T74	Yes	T54,T56,T74	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T31	Yes	T31,T53,T4	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T54,T56,T74	Yes	T54,T56,T74	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T41,T140,T165	Yes	T41,T140,T165	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T41,T140,T165	Yes	T41,T140,T165	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T41,T140,T165	Yes	T41,T140,T165	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T41,T140,T165	Yes	T41,T140,T165	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T41,T140,T42	Yes	T41,T140,T42	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T41,T140,T165	Yes	T41,T140,T165	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T54,*T233,*T56	Yes	T54,T233,T56	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T41,*T140,*T165	Yes	T41,T140,T165	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T41,T140,T165	Yes	T41,T140,T165	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T53,T112,T108	Yes	T53,T112,T108	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T112,T108	Yes	T53,T112,T108	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T80	Yes	T74,T75,T80	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T31,*T53	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T74,T76,T80	Yes	T74,T76,T80	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T79,*T74,*T76	Yes	T79,T74,T75	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T53,*T4,*T88	Yes	T53,T4,T88	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T53,T4,T88	Yes	T53,T4,T88	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T163,T399,T400	Yes	T163,T399,T400	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T163,T399,T400	Yes	T163,T399,T400	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T163,T399,T400	Yes	T163,T399,T400	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T163,T399,T400	Yes	T163,T399,T400	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T75,T80,T122	Yes	T75,T76,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T163,T160,T161	Yes	T163,T160,T161	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T163,T160,T161	Yes	T163,T160,T161	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T163,T160,T161	Yes	T163,T160,T161	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T80	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T163,*T160,*T161	Yes	T163,T399,T400	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T163,T399,T400	Yes	T163,T399,T400	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T31,T53	Yes	T1,T31,T53	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T31,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T31,T4	Yes	T1,T31,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T31,T4	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T31,T4	Yes	T1,T31,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T80	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T77,*T225,*T226	Yes	T77,T225,T226	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T80	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T31	Yes	T2,T3,T31	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T31,T4,T88	Yes	T31,T4,T88	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T31,T4,T88	Yes	T31,T4,T88	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T31,T4,T88	Yes	T31,T4,T88	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T31,T4,T88	Yes	T31,T4,T88	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T76	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T31,T4,T88	Yes	T31,T4,T88	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T4,T88	Yes	T31,T4,T88	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T31,T4,T88	Yes	T31,T4,T88	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T79,*T74,*T75	Yes	T79,T74,T75	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T31,*T4,*T88	Yes	T31,T4,T88	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T31,T4,T88	Yes	T31,T4,T88	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T62,T44,T391	Yes	T62,T44,T391	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T62,T44,T391	Yes	T62,T44,T391	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T62,T44,T391	Yes	T62,T44,T391	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T62,T44,T391	Yes	T62,T44,T391	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T80,T224	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T62,T391,T102	Yes	T62,T391,T102	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T62,T44,T391	Yes	T62,T44,T391	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T62,T44,T391	Yes	T62,T44,T391	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T80,T122	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T74,*T80,*T224	Yes	T74,T75,T80	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T74,T80,T122	Yes	T74,T75,T80	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T62,*T391,*T102	Yes	T62,T44,T391	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T62,T44,T391	Yes	T62,T44,T391	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T53,T112,T44	Yes	T53,T112,T44	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T53,T112,T44	Yes	T53,T112,T44	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T53,T112,T44	Yes	T53,T112,T44	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T53,T112,T44	Yes	T53,T112,T44	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T53,T112,T105	Yes	T53,T112,T44	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T112,T44	Yes	T53,T112,T44	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T53,T112,T44	Yes	T53,T112,T44	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T79,*T74,*T80	Yes	T79,T74,T75	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T53,*T112,*T105	Yes	T53,T112,T44	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T53,T112,T44	Yes	T53,T112,T44	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T54	Yes	T77,T78,T54	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T77,T54,T79	Yes	T77,T54,T79	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T31,T53	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T74,T80,T122	Yes	T74,T75,T80	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T74,T80,T122	Yes	T74,T80,T123	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T74,T75,T80	Yes	T74,T75,T80	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T80	Yes	T74,T75,T80	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range