Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T267,T246,T268
0	1	Covered	T267,T246,T268
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T267,T246,T268
1	Covered	T267,T246,T268

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T267,T246,T268
1	Covered	T267,T246,T268

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T267,T246,T268
1	1	Covered	T267,T246,T268

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T267,T246,T268
1	0	Covered	T267,T246,T268
1	1	Covered	T267,T246,T268

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T267,T246,T268

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T267,T246,T268
0	Covered	T267,T246,T268

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T267,T246,T268
0	Covered	T267,T246,T268

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	744571596	728091344	0	0
CheckNGreaterZero_A	1796	1796	0	0
GntImpliesReady_A	744571596	5454	0	0
GntImpliesValid_A	744571596	5454	0	0
GrantKnown_A	744571596	728091344	0	0
IdxKnown_A	744571596	728091344	0	0
IndexIsCorrect_A	744571596	5454	0	0
NoReadyValidNoGrant_A	744571596	0	0	0
Priority_A	744571596	5454	0	0
ReadyAndValidImplyGrant_A	744571596	5454	0	0
ReqAndReadyImplyGrant_A	744571596	5454	0	0
ReqImpliesValid_A	744571596	5454	0	0
ValidKnown_A	744571596	728091344	0	0
gen_data_port_assertion.DataFlow_A	744571596	5454	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	728091344	0	0
T1	1643728	1642468	0	0
T2	1202376	1202274	0	0
T3	210634	210524	0	0
T4	231816	231652	0	0
T15	1250144	1250020	0	0
T31	344940	344728	0	0
T53	1342446	1342232	0	0
T62	607588	607260	0	0
T87	746826	746716	0	0
T88	290658	290534	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1796	1796	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T15	2	2	0	0
T31	2	2	0	0
T53	2	2	0	0
T62	2	2	0	0
T87	2	2	0	0
T88	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	5454	0	0
T143	302358	0	0	0
T168	337560	0	0	0
T246	0	1820	0	0
T267	166380	1820	0	0
T268	0	1814	0	0
T318	154942	0	0	0
T324	491890	0	0	0
T349	221210	0	0	0
T350	200592	0	0	0
T351	323854	0	0	0
T352	684104	0	0	0
T353	557618	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	5454	0	0
T143	302358	0	0	0
T168	337560	0	0	0
T246	0	1820	0	0
T267	166380	1820	0	0
T268	0	1814	0	0
T318	154942	0	0	0
T324	491890	0	0	0
T349	221210	0	0	0
T350	200592	0	0	0
T351	323854	0	0	0
T352	684104	0	0	0
T353	557618	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	728091344	0	0
T1	1643728	1642468	0	0
T2	1202376	1202274	0	0
T3	210634	210524	0	0
T4	231816	231652	0	0
T15	1250144	1250020	0	0
T31	344940	344728	0	0
T53	1342446	1342232	0	0
T62	607588	607260	0	0
T87	746826	746716	0	0
T88	290658	290534	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	728091344	0	0
T1	1643728	1642468	0	0
T2	1202376	1202274	0	0
T3	210634	210524	0	0
T4	231816	231652	0	0
T15	1250144	1250020	0	0
T31	344940	344728	0	0
T53	1342446	1342232	0	0
T62	607588	607260	0	0
T87	746826	746716	0	0
T88	290658	290534	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	5454	0	0
T143	302358	0	0	0
T168	337560	0	0	0
T246	0	1820	0	0
T267	166380	1820	0	0
T268	0	1814	0	0
T318	154942	0	0	0
T324	491890	0	0	0
T349	221210	0	0	0
T350	200592	0	0	0
T351	323854	0	0	0
T352	684104	0	0	0
T353	557618	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	5454	0	0
T143	302358	0	0	0
T168	337560	0	0	0
T246	0	1820	0	0
T267	166380	1820	0	0
T268	0	1814	0	0
T318	154942	0	0	0
T324	491890	0	0	0
T349	221210	0	0	0
T350	200592	0	0	0
T351	323854	0	0	0
T352	684104	0	0	0
T353	557618	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	5454	0	0
T143	302358	0	0	0
T168	337560	0	0	0
T246	0	1820	0	0
T267	166380	1820	0	0
T268	0	1814	0	0
T318	154942	0	0	0
T324	491890	0	0	0
T349	221210	0	0	0
T350	200592	0	0	0
T351	323854	0	0	0
T352	684104	0	0	0
T353	557618	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	5454	0	0
T143	302358	0	0	0
T168	337560	0	0	0
T246	0	1820	0	0
T267	166380	1820	0	0
T268	0	1814	0	0
T318	154942	0	0	0
T324	491890	0	0	0
T349	221210	0	0	0
T350	200592	0	0	0
T351	323854	0	0	0
T352	684104	0	0	0
T353	557618	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	5454	0	0
T143	302358	0	0	0
T168	337560	0	0	0
T246	0	1820	0	0
T267	166380	1820	0	0
T268	0	1814	0	0
T318	154942	0	0	0
T324	491890	0	0	0
T349	221210	0	0	0
T350	200592	0	0	0
T351	323854	0	0	0
T352	684104	0	0	0
T353	557618	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	728091344	0	0
T1	1643728	1642468	0	0
T2	1202376	1202274	0	0
T3	210634	210524	0	0
T4	231816	231652	0	0
T15	1250144	1250020	0	0
T31	344940	344728	0	0
T53	1342446	1342232	0	0
T62	607588	607260	0	0
T87	746826	746716	0	0
T88	290658	290534	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744571596	5454	0	0
T143	302358	0	0	0
T168	337560	0	0	0
T246	0	1820	0	0
T267	166380	1820	0	0
T268	0	1814	0	0
T318	154942	0	0	0
T324	491890	0	0	0
T349	221210	0	0	0
T350	200592	0	0	0
T351	323854	0	0	0
T352	684104	0	0	0
T353	557618	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T267,T246,T268
0	1	Covered	T267,T246,T268
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T267,T246,T268
1	Covered	T267,T246,T268

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T267,T246,T268
1	Covered	T267,T246,T268

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T267,T246,T268
1	1	Covered	T267,T246,T268

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T267,T246,T268
1	0	Covered	T267,T246,T268
1	1	Covered	T267,T246,T268

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T267,T246,T268

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T267,T246,T268
0	Covered	T267,T246,T268

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T267,T246,T268
0	Covered	T267,T246,T268

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	372285798	364045672	0	0
CheckNGreaterZero_A	898	898	0	0
GntImpliesReady_A	372285798	4416	0	0
GntImpliesValid_A	372285798	4416	0	0
GrantKnown_A	372285798	364045672	0	0
IdxKnown_A	372285798	364045672	0	0
IndexIsCorrect_A	372285798	4416	0	0
NoReadyValidNoGrant_A	372285798	0	0	0
Priority_A	372285798	4416	0	0
ReadyAndValidImplyGrant_A	372285798	4416	0	0
ReqAndReadyImplyGrant_A	372285798	4416	0	0
ReqImpliesValid_A	372285798	4416	0	0
ValidKnown_A	372285798	364045672	0	0
gen_data_port_assertion.DataFlow_A	372285798	4416	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	364045672	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	898	898	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	4416	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	1474	0	0
T267	83190	1474	0	0
T268	0	1468	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	4416	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	1474	0	0
T267	83190	1474	0	0
T268	0	1468	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	364045672	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	364045672	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	4416	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	1474	0	0
T267	83190	1474	0	0
T268	0	1468	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	4416	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	1474	0	0
T267	83190	1474	0	0
T268	0	1468	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	4416	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	1474	0	0
T267	83190	1474	0	0
T268	0	1468	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	4416	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	1474	0	0
T267	83190	1474	0	0
T268	0	1468	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	4416	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	1474	0	0
T267	83190	1474	0	0
T268	0	1468	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	364045672	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	4416	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	1474	0	0
T267	83190	1474	0	0
T268	0	1468	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T267,T246,T268
0	1	Covered	T267,T246,T268
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T267,T246,T268
1	Covered	T267,T246,T268

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T267,T246,T268
1	Covered	T267,T246,T268

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T267,T246,T268
1	1	Covered	T267,T246,T268

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T267,T246,T268
1	0	Covered	T267,T246,T268
1	1	Covered	T267,T246,T268

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T267,T246,T268

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T267,T246,T268
0	Covered	T267,T246,T268

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T267,T246,T268
0	Covered	T267,T246,T268

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	372285798	364045672	0	0
CheckNGreaterZero_A	898	898	0	0
GntImpliesReady_A	372285798	1038	0	0
GntImpliesValid_A	372285798	1038	0	0
GrantKnown_A	372285798	364045672	0	0
IdxKnown_A	372285798	364045672	0	0
IndexIsCorrect_A	372285798	1038	0	0
NoReadyValidNoGrant_A	372285798	0	0	0
Priority_A	372285798	1038	0	0
ReadyAndValidImplyGrant_A	372285798	1038	0	0
ReqAndReadyImplyGrant_A	372285798	1038	0	0
ReqImpliesValid_A	372285798	1038	0	0
ValidKnown_A	372285798	364045672	0	0
gen_data_port_assertion.DataFlow_A	372285798	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	364045672	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	898	898	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T31	1	1	0	0
T53	1	1	0	0
T62	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	1038	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	346	0	0
T267	83190	346	0	0
T268	0	346	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	1038	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	346	0	0
T267	83190	346	0	0
T268	0	346	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	364045672	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	364045672	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	1038	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	346	0	0
T267	83190	346	0	0
T268	0	346	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	1038	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	346	0	0
T267	83190	346	0	0
T268	0	346	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	1038	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	346	0	0
T267	83190	346	0	0
T268	0	346	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	1038	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	346	0	0
T267	83190	346	0	0
T268	0	346	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	1038	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	346	0	0
T267	83190	346	0	0
T268	0	346	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	364045672	0	0
T1	821864	821234	0	0
T2	601188	601137	0	0
T3	105317	105262	0	0
T4	115908	115826	0	0
T15	625072	625010	0	0
T31	172470	172364	0	0
T53	671223	671116	0	0
T62	303794	303630	0	0
T87	373413	373358	0	0
T88	145329	145267	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372285798	1038	0	0
T143	151179	0	0	0
T168	168780	0	0	0
T246	0	346	0	0
T267	83190	346	0	0
T268	0	346	0	0
T318	77471	0	0	0
T324	245945	0	0	0
T349	110605	0	0	0
T350	100296	0	0	0
T351	161927	0	0	0
T352	342052	0	0	0
T353	278809	0	0	0