Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3488941	1			T70	1834		T71	1310		T72	1582
values[2]	720077	1			T71	353		T72	588		T221	51
values[3]	106923	1			T71	17		T72	28		T222	4
values[4]	55397	1			T434	5		T519	4		T517	1
values[5]	36713	1			T434	1		T424	16		T380	303
values[6]	26960	1			T424	16		T380	152		T508	133
values[7]	21735	1			T424	16		T380	109		T508	137
values[8]	18331	1			T424	16		T380	87		T508	115
values[9]	16366	1			T424	16		T380	66		T508	98
values[10]	14842	1			T424	16		T380	63		T508	72
values[11]	13476	1			T424	16		T380	64		T508	71
values[12]	12615	1			T424	16		T380	70		T508	51
values[13]	11961	1			T424	16		T380	63		T508	50
values[14]	11258	1			T424	16		T380	48		T508	61
values[15]	10857	1			T424	16		T380	47		T508	38
values[16]	10298	1			T424	16		T380	66		T508	24
values[17]	9682	1			T424	16		T380	51		T508	15
values[18]	9245	1			T424	16		T380	41		T508	17
values[19]	8859	1			T424	16		T380	39		T508	18
values[20]	8817	1			T424	16		T380	31		T508	35
values[21]	8552	1			T424	16		T380	40		T508	33
values[22]	8414	1			T424	16		T380	41		T508	21
values[23]	8349	1			T424	17		T380	32		T508	19
values[24]	8263	1			T424	16		T380	39		T508	14
values[25]	7736	1			T424	16		T380	20		T508	14
values[26]	7491	1			T424	16		T380	33		T508	17
values[27]	7335	1			T424	17		T380	33		T508	16
values[28]	6658	1			T424	16		T380	25		T508	16
values[29]	6075	1			T424	16		T380	25		T508	11
values[30]	5675	1			T424	16		T380	37		T508	23
values[31]	5453	1			T424	17		T380	32		T508	19
values[32]	5122	1			T424	16		T380	42		T508	25
values[33]	4793	1			T424	16		T380	40		T508	16
values[34]	4508	1			T424	16		T380	44		T508	13
values[35]	4255	1			T424	16		T380	32		T508	20
values[36]	4047	1			T424	16		T380	25		T508	11
values[37]	3759	1			T424	16		T380	27		T508	13
values[38]	3671	1			T424	16		T380	37		T508	9
values[39]	3569	1			T424	16		T380	38		T508	6
values[40]	3413	1			T424	16		T380	40		T508	11
values[41]	3419	1			T424	17		T380	40		T508	15
values[42]	3267	1			T424	16		T380	38		T508	8
values[43]	3161	1			T424	16		T380	35		T508	24
values[44]	3133	1			T424	16		T380	34		T508	28
values[45]	3066	1			T424	17		T380	32		T508	15
values[46]	3089	1			T424	17		T380	20		T508	13
values[47]	3067	1			T424	16		T380	24		T508	15
values[48]	2962	1			T424	16		T380	24		T508	13
values[49]	2947	1			T424	17		T380	30		T508	13
values[50]	2883	1			T424	16		T380	43		T508	12
values[51]	2936	1			T424	16		T380	36		T508	23
values[52]	2747	1			T424	17		T380	20		T508	10
values[53]	2747	1			T424	16		T380	24		T508	11
values[54]	2720	1			T424	16		T380	30		T508	8
values[55]	2609	1			T424	16		T380	22		T508	8
values[56]	2591	1			T424	16		T380	20		T508	12
values[57]	2547	1			T424	16		T380	19		T508	11
values[58]	2536	1			T424	17		T380	21		T508	9
values[59]	2648	1			T424	17		T380	36		T508	13
values[60]	2525	1			T424	17		T380	37		T508	9
values[61]	2852	1			T424	16		T380	44		T508	30
values[62]	4331	1			T424	16		T380	63		T508	68
values[63]	16851	1			T424	17		T380	129		T508	153
values[64]	240649	1			T424	2999		T380	185		T508	158

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4530306	1			T70	1880		T71	1451		T72	1668
values[2]	746156	1			T71	352		T72	443		T221	20
values[3]	75804	1			T71	53		T72	135		T221	2
values[4]	14136	1			T71	4		T72	39		T222	9
values[5]	5630	1			T71	1		T72	8		T424	20
values[6]	3296	1			T72	2		T424	5		T380	25
values[7]	2329	1			T72	1		T424	3		T380	28
values[8]	2027	1			T424	2		T380	26		T508	88
values[9]	1893	1			T424	2		T380	20		T508	67
values[10]	1809	1			T424	2		T380	20		T508	53
values[11]	1519	1			T424	2		T380	16		T508	42
values[12]	1437	1			T424	2		T380	23		T508	39
values[13]	1303	1			T424	2		T380	19		T508	31
values[14]	1130	1			T424	2		T380	6		T508	12
values[15]	1050	1			T424	2		T380	8		T508	9
values[16]	954	1			T424	2		T380	6		T508	20
values[17]	941	1			T424	2		T380	11		T508	10
values[18]	853	1			T424	2		T380	10		T508	8
values[19]	812	1			T424	2		T380	6		T508	7
values[20]	736	1			T424	2		T380	2		T508	4
values[21]	714	1			T424	2		T380	1		T508	1
values[22]	665	1			T424	2		T508	2		T830	2
values[23]	631	1			T424	2		T508	1		T830	2
values[24]	654	1			T424	2		T830	1		T480	3
values[25]	633	1			T424	2		T830	1		T480	5
values[26]	632	1			T424	2		T830	1		T480	6
values[27]	578	1			T424	2		T830	1		T480	5
values[28]	633	1			T424	2		T830	1		T480	4
values[29]	610	1			T424	2		T830	4		T480	6
values[30]	523	1			T424	2		T830	1		T480	7
values[31]	494	1			T424	2		T830	1		T480	9
values[32]	518	1			T424	2		T830	1		T480	4
values[33]	527	1			T424	2		T830	4		T480	9
values[34]	510	1			T424	2		T830	3		T480	5
values[35]	470	1			T424	2		T830	2		T480	5
values[36]	450	1			T424	2		T830	1		T480	5
values[37]	453	1			T424	2		T830	1		T480	4
values[38]	439	1			T424	2		T830	1		T480	5
values[39]	454	1			T424	2		T830	1		T480	4
values[40]	430	1			T424	2		T830	1		T480	8
values[41]	399	1			T424	2		T830	2		T480	5
values[42]	368	1			T424	2		T830	1		T480	5
values[43]	382	1			T424	2		T830	1		T480	4
values[44]	418	1			T424	2		T830	1		T480	8
values[45]	424	1			T424	2		T830	2		T480	15
values[46]	428	1			T424	2		T830	2		T480	11
values[47]	414	1			T424	2		T830	1		T480	4
values[48]	359	1			T424	2		T830	1		T480	7
values[49]	398	1			T424	2		T830	1		T480	3
values[50]	409	1			T424	2		T830	1		T480	3
values[51]	389	1			T424	2		T830	1		T480	3
values[52]	376	1			T424	2		T830	1		T480	6
values[53]	365	1			T424	2		T830	1		T480	3
values[54]	358	1			T424	2		T830	2		T480	8
values[55]	391	1			T424	2		T480	4		T812	2
values[56]	379	1			T424	2		T480	9		T812	2
values[57]	345	1			T424	2		T480	5		T812	2
values[58]	353	1			T424	2		T480	10		T812	2
values[59]	352	1			T424	2		T480	6		T812	2
values[60]	369	1			T424	2		T480	5		T812	2
values[61]	383	1			T424	2		T480	4		T812	2
values[62]	687	1			T424	2		T480	4		T812	2
values[63]	3144	1			T424	2		T480	25		T812	2
values[64]	30055	1			T424	422		T480	404		T812	340

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	594579	1			T70	1803		T71	26		T72	16
values[2]	2430963	1			T71	512		T72	217		T221	77
values[3]	1118006	1			T71	1122		T72	1327		T221	29
values[4]	148912	1			T71	38		T72	248		T222	9
values[5]	75514	1			T71	1		T72	16		T434	66
values[6]	48089	1			T434	34		T424	16		T380	417
values[7]	35189	1			T434	33		T424	16		T380	224
values[8]	27378	1			T434	41		T424	16		T380	141
values[9]	22572	1			T434	25		T424	16		T380	99
values[10]	19791	1			T434	6		T424	16		T380	73
values[11]	17759	1			T424	16		T380	67		T508	138
values[12]	15977	1			T424	16		T380	65		T508	114
values[13]	14615	1			T424	16		T380	55		T508	91
values[14]	13648	1			T424	16		T380	41		T508	89
values[15]	12839	1			T424	16		T380	61		T508	63
values[16]	12153	1			T424	16		T380	67		T508	46
values[17]	11502	1			T424	16		T380	63		T508	33
values[18]	11381	1			T424	16		T380	54		T508	27
values[19]	10853	1			T424	17		T380	46		T508	17
values[20]	10807	1			T424	17		T380	43		T508	21
values[21]	10219	1			T424	16		T380	41		T508	13
values[22]	9815	1			T424	16		T380	35		T508	15
values[23]	9205	1			T424	16		T380	26		T508	23
values[24]	9006	1			T424	16		T380	22		T508	21
values[25]	8685	1			T424	16		T380	31		T508	26
values[26]	8270	1			T424	16		T380	42		T508	15
values[27]	7967	1			T424	16		T380	44		T508	12
values[28]	7468	1			T424	16		T380	41		T508	12
values[29]	7040	1			T424	16		T380	34		T508	11
values[30]	6642	1			T424	16		T380	35		T508	10
values[31]	6046	1			T424	17		T380	46		T508	17
values[32]	5804	1			T424	16		T380	51		T508	21
values[33]	5472	1			T424	16		T380	33		T508	18
values[34]	5084	1			T424	16		T380	33		T508	23
values[35]	4790	1			T424	17		T380	47		T508	15
values[36]	4632	1			T424	16		T380	34		T508	22
values[37]	4372	1			T424	16		T380	28		T508	25
values[38]	4291	1			T424	17		T380	30		T508	14
values[39]	4066	1			T424	16		T380	25		T508	15
values[40]	3957	1			T424	16		T380	23		T508	15
values[41]	3791	1			T424	16		T380	33		T508	16
values[42]	3632	1			T424	16		T380	39		T508	21
values[43]	3812	1			T424	16		T380	25		T508	30
values[44]	3601	1			T424	16		T380	31		T508	27
values[45]	3442	1			T424	16		T380	22		T508	12
values[46]	3488	1			T424	16		T380	35		T508	28
values[47]	3390	1			T424	16		T380	26		T508	12
values[48]	3368	1			T424	16		T380	35		T508	13
values[49]	3305	1			T424	16		T380	53		T508	11
values[50]	3132	1			T424	16		T380	52		T508	20
values[51]	3203	1			T424	16		T380	67		T508	22
values[52]	3106	1			T424	16		T380	48		T508	21
values[53]	3032	1			T424	16		T380	42		T508	11
values[54]	3092	1			T424	16		T380	35		T508	9
values[55]	2911	1			T424	16		T380	24		T508	16
values[56]	2878	1			T424	17		T380	18		T508	5
values[57]	2891	1			T424	16		T380	25		T508	5
values[58]	2768	1			T424	16		T380	31		T508	7
values[59]	2772	1			T424	17		T380	31		T508	7
values[60]	2828	1			T424	16		T380	28		T508	14
values[61]	2949	1			T424	16		T380	26		T508	25
values[62]	4006	1			T424	16		T380	65		T508	53
values[63]	18189	1			T424	267		T380	97		T508	141
values[64]	229524	1			T424	2804		T380	225		T508	155