Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2010566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21573711

1

T1

11012

T2

8873

T3

16393

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15150249	1			T1	4538		T2	4376		T3	7656
values[0x0]	6988522	1			T1	6474		T2	4497		T3	8737
values[0x1]	1445506	1			T1	792		T2	566		T3	1354

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	698140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22886137

1

T1

11804

T2

9439

T3

17747

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10496503	1			T1	5903		T2	4720		T3	8874
valid_sources[0x01]	10496497	1			T1	5901		T2	4719		T3	8873
valid_sources[0x02]	41610	1			T142	3089		T139	333		T334	6274
valid_sources[0x03]	42142	1			T142	3172		T139	382		T334	5869
valid_sources[0x04]	41279	1			T411	2		T142	3176		T139	486
valid_sources[0x05]	41010	1			T77	1		T142	3184		T139	412
valid_sources[0x06]	43051	1			T76	2		T77	11		T411	1
valid_sources[0x07]	41920	1			T411	1		T412	1		T141	6
valid_sources[0x08]	41757	1			T75	1		T76	2		T142	3236
valid_sources[0x09]	42277	1			T411	3		T142	3245		T139	401
valid_sources[0x0a]	41148	1			T411	1		T142	3174		T139	401
valid_sources[0x0b]	41123	1			T411	2		T142	3237		T139	384
valid_sources[0x0c]	41792	1			T142	3200		T139	405		T334	6077
valid_sources[0x0d]	42764	1			T75	2		T142	3276		T139	360
valid_sources[0x0e]	41068	1			T77	1		T411	2		T142	3261
valid_sources[0x0f]	41547	1			T75	1		T411	1		T142	3125
valid_sources[0x10]	41891	1			T142	3233		T139	351		T334	6412
valid_sources[0x11]	41599	1			T411	1		T142	3190		T139	413
valid_sources[0x12]	41396	1			T77	4		T411	1		T412	2
valid_sources[0x13]	41821	1			T75	4		T412	1		T142	3219
valid_sources[0x14]	41529	1			T412	2		T142	3199		T139	426
valid_sources[0x15]	41755	1			T75	3		T77	2		T412	1
valid_sources[0x16]	41761	1			T411	1		T142	3167		T139	456
valid_sources[0x17]	41913	1			T142	3236		T139	407		T334	6349
valid_sources[0x18]	41109	1			T411	1		T412	1		T142	3191
valid_sources[0x19]	41745	1			T76	2		T142	3200		T139	453
valid_sources[0x1a]	41758	1			T75	4		T76	1		T411	1
valid_sources[0x1b]	43842	1			T77	3		T411	2		T412	1
valid_sources[0x1c]	40921	1			T142	3302		T139	378		T334	5778
valid_sources[0x1d]	41454	1			T75	2		T411	1		T142	3166
valid_sources[0x1e]	44160	1			T142	3254		T139	429		T334	6196
valid_sources[0x1f]	42062	1			T142	3315		T139	384		T334	5893
valid_sources[0x20]	41604	1			T411	1		T142	3256		T139	367

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14355779

1

T1

4538

T2

4376

T3

7656

values[0x0]

all_enables

biggest_size

6945295

1

T1

6474

T2

4497

T3

8737

values[0x1]

all_enables

biggest_size

272637

1

T75

19

T76

19

T77

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2735909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

432477

1

T70

239

T71

243

T72

314

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1073337	1			T70	637		T71	555		T72	747
values[0x0]	1022836	1			T70	556		T71	550		T72	744
values[0x1]	1072213	1			T70	641		T71	575		T72	707

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2119446	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1048940

1

T70

606

T71

580

T72

733

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48946	1			T70	12		T71	44		T72	31
valid_sources[0x01]	49025	1			T70	15		T71	32		T72	35
valid_sources[0x02]	48787	1			T71	27		T72	95		T221	9
valid_sources[0x03]	50540	1			T70	16		T71	34		T72	34
valid_sources[0x04]	50261	1			T70	9		T71	25		T72	60
valid_sources[0x05]	49391	1			T70	37		T71	20		T72	17
valid_sources[0x06]	49952	1			T70	70		T71	21		T72	28
valid_sources[0x07]	49943	1			T70	10		T71	27		T72	63
valid_sources[0x08]	49782	1			T70	35		T71	13		T72	40
valid_sources[0x09]	49205	1			T71	24		T72	38		T221	12
valid_sources[0x0a]	49665	1			T70	44		T71	34		T72	46
valid_sources[0x0b]	49984	1			T70	62		T71	37		T72	52
valid_sources[0x0c]	49580	1			T70	37		T71	10		T72	30
valid_sources[0x0d]	49557	1			T70	6		T71	31		T72	10
valid_sources[0x0e]	49136	1			T71	12		T72	44		T222	46
valid_sources[0x0f]	49817	1			T70	41		T71	8		T72	25
valid_sources[0x10]	49369	1			T70	36		T71	23		T72	10
valid_sources[0x11]	49131	1			T70	21		T71	30		T72	64
valid_sources[0x12]	48892	1			T70	62		T71	18		T72	9
valid_sources[0x13]	49787	1			T70	28		T71	11		T72	52
valid_sources[0x14]	49212	1			T70	47		T71	29		T72	51
valid_sources[0x15]	50130	1			T70	70		T71	29		T72	23
valid_sources[0x16]	51102	1			T70	37		T71	17		T72	62
valid_sources[0x17]	49920	1			T71	15		T72	32		T222	51
valid_sources[0x18]	48945	1			T70	25		T71	18		T72	10
valid_sources[0x19]	49368	1			T70	13		T71	26		T72	21
valid_sources[0x1a]	50636	1			T71	16		T72	30		T221	5
valid_sources[0x1b]	49462	1			T70	32		T71	18		T72	26
valid_sources[0x1c]	49285	1			T70	30		T71	54		T72	67
valid_sources[0x1d]	50298	1			T70	7		T71	28		T72	31
valid_sources[0x1e]	49981	1			T70	29		T71	30		T72	31
valid_sources[0x1f]	49375	1			T70	14		T71	73		T72	20
valid_sources[0x20]	49607	1			T70	9		T71	16		T72	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45707

1

T70

23

T71

22

T72

35

values[0x0]

all_enables

biggest_size

341195

1

T70

186

T71

196

T72

236

values[0x1]

all_enables

biggest_size

45575

1

T70

30

T71

25

T72

43

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2909702	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

473187

1

T70

266

T71

251

T72

317

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1158850	1			T70	644		T71	652		T72	738
values[0x0]	1066773	1			T70	592		T71	570		T72	771
values[0x1]	1157266	1			T70	644		T71	639		T72	787

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2232005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1150884

1

T70

646

T71

602

T72

784

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52314	1			T70	14		T71	36		T72	50
valid_sources[0x01]	53097	1			T70	11		T71	23		T72	18
valid_sources[0x02]	52301	1			T71	30		T72	54		T221	2
valid_sources[0x03]	53222	1			T70	15		T71	48		T72	50
valid_sources[0x04]	53675	1			T70	16		T71	15		T72	58
valid_sources[0x05]	52251	1			T70	29		T71	39		T72	29
valid_sources[0x06]	53108	1			T70	72		T71	43		T72	23
valid_sources[0x07]	52881	1			T70	10		T71	22		T72	75
valid_sources[0x08]	52479	1			T70	36		T71	44		T72	13
valid_sources[0x09]	52195	1			T71	38		T72	46		T221	4
valid_sources[0x0a]	52958	1			T70	35		T71	16		T72	30
valid_sources[0x0b]	52428	1			T70	43		T71	15		T72	59
valid_sources[0x0c]	52290	1			T70	41		T71	20		T72	40
valid_sources[0x0d]	53183	1			T70	16		T71	42		T72	39
valid_sources[0x0e]	53867	1			T71	29		T72	43		T221	3
valid_sources[0x0f]	53316	1			T70	52		T71	17		T72	31
valid_sources[0x10]	53202	1			T70	48		T71	17		T72	56
valid_sources[0x11]	52204	1			T70	36		T71	22		T72	24
valid_sources[0x12]	52799	1			T70	51		T71	10		T72	34
valid_sources[0x13]	52409	1			T70	27		T71	25		T72	27
valid_sources[0x14]	53210	1			T70	26		T71	29		T72	37
valid_sources[0x15]	53291	1			T70	59		T71	12		T72	50
valid_sources[0x16]	53722	1			T70	31		T71	30		T72	33
valid_sources[0x17]	52371	1			T71	50		T72	58		T221	3
valid_sources[0x18]	52371	1			T70	30		T71	25		T72	47
valid_sources[0x19]	52854	1			T70	12		T71	21		T72	34
valid_sources[0x1a]	52042	1			T71	20		T72	24		T221	2
valid_sources[0x1b]	52327	1			T70	32		T71	40		T72	31
valid_sources[0x1c]	52618	1			T70	22		T71	18		T72	48
valid_sources[0x1d]	53311	1			T70	13		T71	42		T72	20
valid_sources[0x1e]	53029	1			T70	33		T71	33		T72	30
valid_sources[0x1f]	52292	1			T70	18		T71	17		T72	31
valid_sources[0x20]	52694	1			T70	10		T71	26		T72	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49814

1

T70

21

T71

24

T72

26

values[0x0]

all_enables

biggest_size

373923

1

T70

226

T71

195

T72

264

values[0x1]

all_enables

biggest_size

49450

1

T70

19

T71

32

T72

27

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2758279	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

435851

1

T70

222

T71

219

T72

243

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1081639	1			T70	589		T71	575		T72	632
values[0x0]	1030936	1			T70	592		T71	518		T72	547
values[0x1]	1081555	1			T70	622		T71	606		T72	645

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2136052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1058078

1

T70

559

T71

568

T72

637

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49598	1			T70	11		T71	26		T72	19
valid_sources[0x01]	49892	1			T70	16		T71	21		T72	15
valid_sources[0x02]	49990	1			T71	19		T72	40		T221	3
valid_sources[0x03]	49982	1			T70	11		T71	28		T72	42
valid_sources[0x04]	50553	1			T70	18		T71	34		T72	27
valid_sources[0x05]	49825	1			T70	31		T71	23		T72	37
valid_sources[0x06]	49903	1			T70	53		T71	24		T72	17
valid_sources[0x07]	49820	1			T70	6		T71	34		T72	38
valid_sources[0x08]	49745	1			T70	21		T71	36		T72	23
valid_sources[0x09]	49677	1			T71	22		T72	19		T221	2
valid_sources[0x0a]	50596	1			T70	38		T71	23		T72	16
valid_sources[0x0b]	50202	1			T70	56		T71	23		T72	16
valid_sources[0x0c]	49476	1			T70	32		T71	25		T72	30
valid_sources[0x0d]	50006	1			T70	17		T71	21		T72	33
valid_sources[0x0e]	49948	1			T71	32		T72	50		T222	29
valid_sources[0x0f]	49715	1			T70	30		T71	20		T72	28
valid_sources[0x10]	49969	1			T70	40		T71	25		T72	28
valid_sources[0x11]	49977	1			T70	31		T71	28		T72	23
valid_sources[0x12]	49728	1			T70	57		T71	29		T72	20
valid_sources[0x13]	49694	1			T70	20		T71	27		T72	18
valid_sources[0x14]	50205	1			T70	44		T71	32		T72	18
valid_sources[0x15]	50453	1			T70	58		T71	24		T72	32
valid_sources[0x16]	50863	1			T70	28		T71	27		T72	23
valid_sources[0x17]	50028	1			T71	28		T72	29		T222	37
valid_sources[0x18]	50085	1			T70	24		T71	30		T72	23
valid_sources[0x19]	49791	1			T70	10		T71	29		T72	52
valid_sources[0x1a]	50105	1			T71	29		T72	27		T222	41
valid_sources[0x1b]	49137	1			T70	35		T71	29		T72	28
valid_sources[0x1c]	50086	1			T70	31		T71	30		T72	22
valid_sources[0x1d]	49860	1			T70	20		T71	24		T72	20
valid_sources[0x1e]	49153	1			T70	52		T71	41		T72	22
valid_sources[0x1f]	50287	1			T70	6		T71	36		T72	29
valid_sources[0x20]	48622	1			T70	6		T71	20		T72	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45665

1

T70

20

T71

28

T72

30

values[0x0]

all_enables

biggest_size

344368

1

T70

179

T71

173

T72

188

values[0x1]

all_enables

biggest_size

45818

1

T70

23

T71

18

T72

25