Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.25			94.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	94.19			94.19
tb.dut.top_earlgrey.u_i2c1	94.22			94.22
tb.dut.top_earlgrey.u_i2c2	94.22			94.22

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.19			94.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.19			94.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	348	328	94.25
Total Bits 0->1	174	164	94.25
Total Bits 1->0	174	164	94.25

Ports	52	48	92.31
Port Bits	348	328	94.25
Port Bits 0->1	174	164	94.25
Port Bits 1->0	174	164	94.25

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T227,T348,T306	Yes	T227,T348,T306	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T227,T348,T306	Yes	T227,T348,T306	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T65,*T73,*T74	Yes	T65,T73,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	INPUT
tl_o.a_ready	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T227,T306,T325	Yes	T227,T306,T325	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T227,T348,T306	Yes	T227,T55,T348	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T227,T348,T306	Yes	T227,T55,T348	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T227,*T348,*T306	Yes	T227,T348,T306	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T192,T349,T350	Yes	T192,T349,T350	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T192,T79,T80	Yes	T192,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T192,T79,T80	Yes	T192,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T192,T349,T350	Yes	T192,T349,T350	OUTPUT
cio_scl_i	Yes	Yes	T306,T325,T178	Yes	T306,T325,T178	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T306,T178,T311	Yes	T306,T178,T311	OUTPUT
cio_sda_i	Yes	Yes	T306,T325,T178	Yes	T306,T325,T178	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T306,T325,T178	Yes	T306,T325,T178	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T227,T306,T178	Yes	T227,T306,T178	OUTPUT
intr_rx_threshold_o	Yes	Yes	T227,T306,T178	Yes	T227,T306,T178	OUTPUT
intr_acq_threshold_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_rx_overflow_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_controller_halt_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_scl_interference_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_sda_interference_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_sda_unstable_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_cmd_complete_o	Yes	Yes	T227,T306,T325	Yes	T227,T306,T325	OUTPUT
intr_tx_stretch_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_tx_threshold_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_acq_stretch_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_unexp_stop_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_host_timeout_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	344	324	94.19
Total Bits 0->1	172	162	94.19
Total Bits 1->0	172	162	94.19

Ports	52	48	92.31
Port Bits	344	324	94.19
Port Bits 0->1	172	162	94.19
Port Bits 1->0	172	162	94.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T227,T348,T178	Yes	T227,T348,T178	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T227,T348,T178	Yes	T227,T348,T178	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T65,*T73,*T74	Yes	T65,T73,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	INPUT
tl_o.a_ready	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T227,T178,T179	Yes	T227,T178,T179	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T227,T348,T178	Yes	T227,T55,T348	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T227,T348,T178	Yes	T227,T55,T348	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T227,*T348,*T178	Yes	T227,T348,T178	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T192,T350,T55	Yes	T192,T350,T55	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T192,T79,T80	Yes	T192,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T192,T79,T80	Yes	T192,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T192,T350,T55	Yes	T192,T350,T55	OUTPUT
cio_scl_i	Yes	Yes	T178,T179,T351	Yes	T178,T179,T351	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T178,T179,T351	Yes	T178,T179,T351	OUTPUT
cio_sda_i	Yes	Yes	T178,T179,T351	Yes	T178,T179,T351	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T178,T179,T351	Yes	T178,T179,T351	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T227,T178,T179	Yes	T227,T178,T179	OUTPUT
intr_rx_threshold_o	Yes	Yes	T227,T178,T179	Yes	T227,T178,T179	OUTPUT
intr_acq_threshold_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_rx_overflow_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_controller_halt_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_scl_interference_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_sda_interference_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_sda_unstable_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_cmd_complete_o	Yes	Yes	T227,T178,T179	Yes	T227,T178,T179	OUTPUT
intr_tx_stretch_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_tx_threshold_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_acq_stretch_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_unexp_stop_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_host_timeout_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	346	326	94.22
Total Bits 0->1	173	163	94.22
Total Bits 1->0	173	163	94.22

Ports	52	48	92.31
Port Bits	346	326	94.22
Port Bits 0->1	173	163	94.22
Port Bits 1->0	173	163	94.22

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T227,T348,T306	Yes	T227,T348,T306	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T227,T348,T306	Yes	T227,T348,T306	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T65,*T73,*T74	Yes	T65,T73,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	INPUT
tl_o.a_ready	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T227,T306,T325	Yes	T227,T306,T325	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T227,T348,T306	Yes	T227,T55,T348	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T227,T348,T306	Yes	T227,T55,T348	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T227,*T348,*T306	Yes	T227,T348,T306	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T192,T349,T55	Yes	T192,T349,T55	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T192,T79,T80	Yes	T192,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T192,T79,T80	Yes	T192,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T192,T349,T55	Yes	T192,T349,T55	OUTPUT
cio_scl_i	Yes	Yes	T306,T325,T311	Yes	T306,T325,T311	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T306,T311,T352	Yes	T306,T311,T352	OUTPUT
cio_sda_i	Yes	Yes	T306,T325,T311	Yes	T306,T325,T311	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T306,T325,T311	Yes	T306,T325,T311	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T227,T306,T311	Yes	T227,T306,T311	OUTPUT
intr_rx_threshold_o	Yes	Yes	T227,T306,T311	Yes	T227,T306,T311	OUTPUT
intr_acq_threshold_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_rx_overflow_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_controller_halt_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_scl_interference_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_sda_interference_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_sda_unstable_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_cmd_complete_o	Yes	Yes	T227,T306,T325	Yes	T227,T306,T325	OUTPUT
intr_tx_stretch_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_tx_threshold_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_acq_stretch_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_unexp_stop_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_host_timeout_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	346	326	94.22
Total Bits 0->1	173	163	94.22
Total Bits 1->0	173	163	94.22

Ports	52	48	92.31
Port Bits	346	326	94.22
Port Bits 0->1	173	163	94.22
Port Bits 1->0	173	163	94.22

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T227,T348,T312	Yes	T227,T348,T312	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T227,T348,T312	Yes	T227,T348,T312	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T65,*T73,*T74	Yes	T65,T73,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_valid	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	INPUT
tl_o.a_ready	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T227,T312,T301	Yes	T227,T312,T301	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T227,T348,T312	Yes	T227,T55,T348	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T227,T348,T312	Yes	T227,T55,T348	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T227,*T348,*T312	Yes	T227,T348,T312	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T227,T55,T348	Yes	T227,T55,T348	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T192,T55,T353	Yes	T192,T55,T353	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T192,T79,T80	Yes	T192,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T192,T79,T80	Yes	T192,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T192,T55,T353	Yes	T192,T55,T353	OUTPUT
cio_scl_i	Yes	Yes	T312,T354,T355	Yes	T312,T354,T355	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T312,T355,T356	Yes	T312,T355,T356	OUTPUT
cio_sda_i	Yes	Yes	T312,T354,T355	Yes	T312,T354,T355	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T312,T354,T355	Yes	T312,T354,T355	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T227,T312,T301	Yes	T227,T312,T301	OUTPUT
intr_rx_threshold_o	Yes	Yes	T227,T312,T301	Yes	T227,T312,T301	OUTPUT
intr_acq_threshold_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_rx_overflow_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_controller_halt_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_scl_interference_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_sda_interference_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_sda_unstable_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_cmd_complete_o	Yes	Yes	T227,T312,T301	Yes	T227,T312,T301	OUTPUT
intr_tx_stretch_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_tx_threshold_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_acq_stretch_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_unexp_stop_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT
intr_host_timeout_o	Yes	Yes	T227,T301,T302	Yes	T227,T301,T302	OUTPUT

*Tests covering at least one bit in the range