Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_host
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.53 95.53

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_spi_host1 96.30 96.30
tb.dut.top_earlgrey.u_spi_host0 96.59 96.59



Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 96.30


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 96.30


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 96.59


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 96.59


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : spi_host
TotalCoveredPercent
Totals 46 42 91.30
Total Bits 358 342 95.53
Total Bits 0->1 179 171 95.53
Total Bits 1->0 179 171 95.53

Ports 46 42 91.30
Port Bits 358 342 95.53
Port Bits 0->1 179 171 95.53
Port Bits 1->0 179 171 95.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T34 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_mask[3:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_address[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T146,*T35,*T36 Yes T146,T35,T36 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T146,*T10,*T11 Yes T146,T10,T11 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T10,T12,T176 Yes T10,T12,T176 INPUT
tl_i.a_valid Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_o.a_ready Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
tl_o.d_error Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
tl_o.d_data[31:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
tl_o.d_sink Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T146,*T10,*T11 Yes T146,T10,T11 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T252,T192 Yes T2,T252,T192 INPUT
alert_rx_i[0].ping_n Yes Yes T2,T192,T287 Yes T2,T192,T287 INPUT
alert_rx_i[0].ping_p Yes Yes T2,T192,T287 Yes T2,T192,T287 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T252,T192 Yes T2,T252,T192 OUTPUT
cio_sck_o Yes Yes T10,T11,T35 Yes T10,T11,T35 OUTPUT
cio_sck_en_o Yes Yes T10,T11,T12 Yes T10,T11,T35 OUTPUT
cio_csb_o Yes Yes T10,T11,T35 Yes T10,T11,T35 OUTPUT
cio_csb_en_o Yes Yes T10,T11,T12 Yes T10,T11,T35 OUTPUT
cio_sd_o[3:0] Yes Yes T10,T11,T35 Yes T10,T11,T35 OUTPUT
cio_sd_en_o[0] Yes Yes *T10,*T11,*T35 Yes T10,T11,T35 OUTPUT
cio_sd_en_o[3:1] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T10,T11,T35 Yes T10,T11,T35 INPUT
passthrough_i.s_en[0] Yes Yes *T10,*T11,*T12 Yes T10,T11,T12 INPUT
passthrough_i.s_en[3:1] No No No INPUT
passthrough_i.s[3:0] Yes Yes T65,T41,T10 Yes T65,T41,T10 INPUT
passthrough_i.csb_en No No No INPUT
passthrough_i.csb Yes Yes T45,T46,T65 Yes T65,T10,T73 INPUT
passthrough_i.sck_en No No No INPUT
passthrough_i.sck Yes Yes T65,T41,T10 Yes T65,T41,T10 INPUT
passthrough_i.passthrough_en Yes Yes T10,T12,T176 Yes T10,T11,T12 INPUT
passthrough_o.s[3:0] Yes Yes T10,T11,T35 Yes T10,T11,T35 OUTPUT
intr_error_o Yes Yes T146,T147,T148 Yes T146,T147,T148 OUTPUT
intr_spi_event_o Yes Yes T146,T147,T148 Yes T146,T147,T148 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1
TotalCoveredPercent
Totals 38 36 94.74
Total Bits 324 312 96.30
Total Bits 0->1 162 156 96.30
Total Bits 1->0 162 156 96.30

Ports 38 36 94.74
Port Bits 324 312 96.30
Port Bits 0->1 162 156 96.30
Port Bits 1->0 162 156 96.30

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T34 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T146,T35,T36 Yes T146,T35,T36 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T146,T35,T36 Yes T146,T35,T36 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T146,T35,T36 Yes T146,T35,T36 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T146,T35,T36 Yes T146,T35,T36 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T146,T35,T36 Yes T146,T35,T36 INPUT
tl_i.a_mask[3:0] Yes Yes T146,T35,T36 Yes T146,T35,T36 INPUT
tl_i.a_address[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T146,*T35,*T36 Yes T146,T35,T36 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T146,T35,T36 Yes T146,T35,T36 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T146,*T35,*T36 Yes T146,T35,T36 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_i.a_valid Yes Yes T146,T35,T36 Yes T146,T35,T36 INPUT
tl_o.a_ready Yes Yes T146,T35,T36 Yes T146,T35,T36 OUTPUT
tl_o.d_error Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T146,T35,T36 Yes T146,T35,T36 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T146,T35,T36 Yes T146,T35,T36 OUTPUT
tl_o.d_data[31:0] Yes Yes T146,T35,T36 Yes T146,T35,T36 OUTPUT
tl_o.d_sink Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T146,*T35,*T36 Yes T146,T35,T36 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T146,T35,T36 Yes T146,T35,T36 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T252,T192 Yes T2,T252,T192 INPUT
alert_rx_i[0].ping_n Yes Yes T2,T192,T287 Yes T2,T192,T287 INPUT
alert_rx_i[0].ping_p Yes Yes T2,T192,T287 Yes T2,T192,T287 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T252,T192 Yes T2,T252,T192 OUTPUT
cio_sck_o Yes Yes T35,T36 Yes T35,T36 OUTPUT
cio_sck_en_o Yes Yes T139,T334,T127 Yes T35,T36,T139 OUTPUT
cio_csb_o Yes Yes T35,T36 Yes T35,T36 OUTPUT
cio_csb_en_o Yes Yes T139,T334,T127 Yes T35,T36,T139 OUTPUT
cio_sd_o[0] Yes Yes *T35,*T36 Yes T35,T36 OUTPUT
cio_sd_o[3:1] No No No OUTPUT
cio_sd_en_o[0] Yes Yes *T35,*T36 Yes T35,T36 OUTPUT
cio_sd_en_o[3:1] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T35,T36,T357 Yes T35,T36,T37 INPUT
passthrough_i.s_en[3:0] Unreachable Unreachable Unreachable INPUT
passthrough_i.s[3:0] Unreachable Unreachable Unreachable INPUT
passthrough_i.csb_en Unreachable Unreachable Unreachable INPUT
passthrough_i.csb Unreachable Unreachable Unreachable INPUT
passthrough_i.sck_en Unreachable Unreachable Unreachable INPUT
passthrough_i.sck Unreachable Unreachable Unreachable INPUT
passthrough_i.passthrough_en Unreachable Unreachable Unreachable INPUT
passthrough_o.s[3:0] Unreachable Unreachable Unreachable OUTPUT
intr_error_o Yes Yes T146,T147,T148 Yes T146,T147,T148 OUTPUT
intr_spi_event_o Yes Yes T146,T147,T148 Yes T146,T147,T148 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0
TotalCoveredPercent
Totals 44 42 95.45
Total Bits 352 340 96.59
Total Bits 0->1 176 170 96.59
Total Bits 1->0 176 170 96.59

Ports 44 42 95.45
Port Bits 352 340 96.59
Port Bits 0->1 176 170 96.59
Port Bits 1->0 176 170 96.59

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T34 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_mask[3:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_address[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_address[19:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T146,*T10,*T11 Yes T146,T10,T11 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T10,T12,T176 Yes T10,T12,T176 INPUT
tl_i.a_valid Yes Yes T146,T10,T11 Yes T146,T10,T11 INPUT
tl_o.a_ready Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
tl_o.d_error Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
tl_o.d_data[31:0] Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
tl_o.d_sink Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T146,*T10,*T11 Yes T146,T10,T11 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T146,T10,T11 Yes T146,T10,T11 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T192,T55,T287 Yes T192,T55,T287 INPUT
alert_rx_i[0].ping_n Yes Yes T192,T287,T79 Yes T192,T287,T79 INPUT
alert_rx_i[0].ping_p Yes Yes T192,T287,T79 Yes T192,T287,T79 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T192,T55,T287 Yes T192,T55,T287 OUTPUT
cio_sck_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_sck_en_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_csb_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_csb_en_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_sd_o[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_sd_en_o[0] Yes Yes *T10,*T11,*T12 Yes T10,T11,T12 OUTPUT
cio_sd_en_o[3:1] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
passthrough_i.s_en[0] Yes Yes *T10,*T11,*T12 Yes T10,T11,T12 INPUT
passthrough_i.s_en[3:1] No No No INPUT
passthrough_i.s[3:0] Yes Yes T65,T41,T10 Yes T65,T41,T10 INPUT
passthrough_i.csb_en[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off.
passthrough_i.csb Yes Yes T45,T46,T65 Yes T65,T10,T73 INPUT
passthrough_i.sck_en[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off.
passthrough_i.sck Yes Yes T65,T41,T10 Yes T65,T41,T10 INPUT
passthrough_i.passthrough_en Yes Yes T10,T12,T176 Yes T10,T11,T12 INPUT
passthrough_o.s[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
intr_error_o Yes Yes T146,T147,T148 Yes T146,T147,T148 OUTPUT
intr_spi_event_o Yes Yes T146,T147,T148 Yes T146,T147,T148 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%