Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	368981338	38187238	0	0
DepthKnown_A	368981338	368887374	0	0
RvalidKnown_A	368981338	368887374	0	0
WreadyKnown_A	368981338	368887374	0	0
gen_passthru_fifo.paramCheckPass	871	871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	38187238	0	0
T1	281555	19938	0	0
T2	160451	24588	0	0
T3	268100	35063	0	0
T16	99027	11092	0	0
T34	290689	31659	0	0
T44	35585	0	0	0
T59	519167	737059	0	0
T82	42251	3461	0	0
T83	84902	9021	0	0
T84	102639	13305	0	0
T110	0	11248	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	871	871	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	368981338	29196518	0	0
DepthKnown_A	368981338	368887374	0	0
RvalidKnown_A	368981338	368887374	0	0
WreadyKnown_A	368981338	368887374	0	0
gen_passthru_fifo.paramCheckPass	871	871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	29196518	0	0
T1	281555	15872	0	0
T2	160451	17876	0	0
T3	268100	25317	0	0
T16	99027	8644	0	0
T34	290689	24196	0	0
T44	35585	0	0	0
T59	519167	730895	0	0
T82	42251	1867	0	0
T83	84902	6857	0	0
T84	102639	10086	0	0
T110	0	8814	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	871	871	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	368981338	21321579	0	0
DepthKnown_A	368981338	368887374	0	0
RvalidKnown_A	368981338	368887374	0	0
WreadyKnown_A	368981338	368887374	0	0
gen_passthru_fifo.paramCheckPass	871	871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	21321579	0	0
T1	281555	12056	0	0
T2	160451	9710	0	0
T3	268100	18137	0	0
T16	99027	5494	0	0
T34	290689	17929	0	0
T44	35585	0	0	0
T59	519167	11650	0	0
T82	42251	459	0	0
T83	84902	4576	0	0
T84	102639	6647	0	0
T110	0	5902	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	871	871	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	368981338	20998456	0	0
DepthKnown_A	368981338	368887374	0	0
RvalidKnown_A	368981338	368887374	0	0
WreadyKnown_A	368981338	368887374	0	0
gen_passthru_fifo.paramCheckPass	871	871	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	20998456	0	0
T1	281555	11804	0	0
T2	160451	9439	0	0
T3	268100	17747	0	0
T16	99027	5359	0	0
T34	290689	17488	0	0
T44	35585	0	0	0
T59	519167	11293	0	0
T82	42251	351	0	0
T83	84902	4434	0	0
T84	102639	6497	0	0
T110	0	5759	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	368887374	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	871	871	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462545472	89573	0	0
DepthKnown_A	462545472	462439346	0	0
RvalidKnown_A	462545472	462439346	0	0
WreadyKnown_A	462545472	462439346	0	0
gen_passthru_fifo.paramCheckPass	2762	2762	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	89573	0	0
T1	281555	29	0	0
T2	160451	26	0	0
T3	268100	150	0	0
T16	99027	13	0	0
T34	290689	64	0	0
T44	35585	0	0	0
T59	519167	30	0	0
T82	42251	8	0	0
T83	84902	13	0	0
T84	102639	16	0	0
T110	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2762	2762	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462545472	91130	0	0
DepthKnown_A	462545472	462439346	0	0
RvalidKnown_A	462545472	462439346	0	0
WreadyKnown_A	462545472	462439346	0	0
gen_passthru_fifo.paramCheckPass	2762	2762	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	91130	0	0
T1	281555	29	0	0
T2	160451	26	0	0
T3	268100	150	0	0
T16	99027	13	0	0
T34	290689	64	0	0
T44	35585	0	0	0
T59	519167	30	0	0
T82	42251	8	0	0
T83	84902	13	0	0
T84	102639	16	0	0
T110	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2762	2762	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462545472	46681	0	0
DepthKnown_A	462545472	462439346	0	0
RvalidKnown_A	462545472	462439346	0	0
WreadyKnown_A	462545472	462439346	0	0
gen_passthru_fifo.paramCheckPass	2762	2762	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	46681	0	0
T1	281555	25	0	0
T2	160451	23	0	0
T3	268100	95	0	0
T16	99027	12	0	0
T34	290689	59	0	0
T44	35585	0	0	0
T59	519167	24	0	0
T82	42251	8	0	0
T83	84902	12	0	0
T84	102639	13	0	0
T110	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2762	2762	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462545472	46681	0	0
DepthKnown_A	462545472	462439346	0	0
RvalidKnown_A	462545472	462439346	0	0
WreadyKnown_A	462545472	462439346	0	0
gen_passthru_fifo.paramCheckPass	2762	2762	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	46681	0	0
T1	281555	25	0	0
T2	160451	23	0	0
T3	268100	95	0	0
T16	99027	12	0	0
T34	290689	59	0	0
T44	35585	0	0	0
T59	519167	24	0	0
T82	42251	8	0	0
T83	84902	12	0	0
T84	102639	13	0	0
T110	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2762	2762	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462545472	42892	0	0
DepthKnown_A	462545472	462439346	0	0
RvalidKnown_A	462545472	462439346	0	0
WreadyKnown_A	462545472	462439346	0	0
gen_passthru_fifo.paramCheckPass	2762	2762	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	42892	0	0
T1	281555	4	0	0
T2	160451	3	0	0
T3	268100	55	0	0
T4	0	4	0	0
T16	99027	1	0	0
T34	290689	5	0	0
T44	35585	0	0	0
T59	519167	6	0	0
T82	42251	0	0	0
T83	84902	1	0	0
T84	102639	3	0	0
T110	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2762	2762	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462545472	44449	0	0
DepthKnown_A	462545472	462439346	0	0
RvalidKnown_A	462545472	462439346	0	0
WreadyKnown_A	462545472	462439346	0	0
gen_passthru_fifo.paramCheckPass	2762	2762	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	44449	0	0
T1	281555	4	0	0
T2	160451	3	0	0
T3	268100	55	0	0
T4	0	4	0	0
T16	99027	1	0	0
T34	290689	5	0	0
T44	35585	0	0	0
T59	519167	6	0	0
T82	42251	0	0	0
T83	84902	1	0	0
T84	102639	3	0	0
T110	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462545472	462439346	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2762	2762	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0