Unified Coverage Report :: Module :: sensor_ctrl

Module : sensor_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22	92.86	87.00	91.23		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon	94.22	92.86	87.00	91.23		100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22	92.86	87.00	91.23		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.29	93.07	87.32	91.23		94.85	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_sync_assign[0].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[10].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[1].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[2].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[3].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[4].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[5].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[6].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[7].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[8].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[9].u_alert_in_buf	100.00	100.00
u_alert_n_sync	100.00	100.00				100.00
u_alert_p_sync	100.00	100.00				100.00
u_init_chg	100.00	100.00	100.00			100.00
u_init_intr	100.00	100.00	100.00			100.00	100.00
u_io_intr	100.00	100.00	100.00			100.00	100.00
u_io_status_chg	100.00	100.00				100.00
u_prim_sec_anchor_buf	100.00	100.00
u_reg	93.46	92.46	86.89			94.47	100.00
u_wake_sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl

	Line No.	Total	Covered	Percent
TOTAL		84	78	92.86
ALWAYS	183	0	0
ALWAYS	183	2	2	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	241	0	0
ALWAYS	241	3	3	100.00
ALWAYS	249	0	0
ALWAYS	249	3	3	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
ALWAYS	327	3	3	100.00
ALWAYS	338	3	3	100.00
CONT_ASSIGN	349	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
183	1	1
184	1	1
208	11	11
211	11	11
214	11	11
219	11	11
222	5	11
225	11	11
231	1	1
241	1	1
242	1	1
243	1	1
249	1	1
250	1	1
251	1	1
258	1	1
260	1	1
311	1	1
327	1	1
328	1	1
330	1	1
338	1	1
339	1	1
341	1	1
349		unreachable

---

Cond Coverage for Module : sensor_ctrl

	Total	Covered	Percent
Conditions	100	87	87.00
Logical	100	87	87.00
Non-Logical	0	0
Event	0	0

 LINE       184
 EXPRESSION (alert_event_p[i] | ((~alert_event_n[i])))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T123,T124,T125
0	1	Not Covered
1	0	Not Covered

 LINE       211
 EXPRESSION (alert_en_buf[0] && event_vld[0] && ((!reg2hw.fatal_alert_en[0])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T129
1	0	1	Covered	T123,T124,T125
1	1	0	Covered	T129,T130,T131
1	1	1	Covered	T123,T124,T125

 LINE       211
 EXPRESSION (alert_en_buf[1] && event_vld[1] && ((!reg2hw.fatal_alert_en[1])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T126
1	0	1	Covered	T123,T124,T125
1	1	0	Covered	T126
1	1	1	Covered	T123,T124,T126

 LINE       211
 EXPRESSION (alert_en_buf[2] && event_vld[2] && ((!reg2hw.fatal_alert_en[2])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T129
1	0	1	Covered	T123,T124,T125
1	1	0	Covered	T129,T130,T131
1	1	1	Covered	T123,T124,T129

 LINE       211
 EXPRESSION (alert_en_buf[3] && event_vld[3] && ((!reg2hw.fatal_alert_en[3])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T132
1	0	1	Covered	T123,T124,T125
1	1	0	Not Covered
1	1	1	Covered	T123,T124,T132

 LINE       211
 EXPRESSION (alert_en_buf[4] && event_vld[4] && ((!reg2hw.fatal_alert_en[4])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T126
1	0	1	Covered	T123,T124,T125
1	1	0	Covered	T126,T129,T130
1	1	1	Covered	T123,T124,T126

 LINE       211
 EXPRESSION (alert_en_buf[5] && event_vld[5] && ((!reg2hw.fatal_alert_en[5])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T134
1	0	1	Covered	T123,T124,T125
1	1	0	Covered	T134
1	1	1	Covered	T123,T124,T134

 LINE       211
 EXPRESSION (alert_en_buf[6] && event_vld[6] && ((!reg2hw.fatal_alert_en[6])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T132
1	0	1	Covered	T123,T124,T125
1	1	0	Not Covered
1	1	1	Covered	T123,T124,T132

 LINE       211
 EXPRESSION (alert_en_buf[7] && event_vld[7] && ((!reg2hw.fatal_alert_en[7])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T132
1	0	1	Covered	T123,T124,T125
1	1	0	Not Covered
1	1	1	Covered	T123,T124,T106

 LINE       211
 EXPRESSION (alert_en_buf[8] && event_vld[8] && ((!reg2hw.fatal_alert_en[8])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T132
1	0	1	Covered	T123,T124,T125
1	1	0	Not Covered
1	1	1	Covered	T123,T124,T106

 LINE       211
 EXPRESSION (alert_en_buf[9] && event_vld[9] && ((!reg2hw.fatal_alert_en[9])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T132
1	0	1	Covered	T123,T124,T125
1	1	0	Not Covered
1	1	1	Covered	T123,T124,T132

 LINE       211
 EXPRESSION (alert_en_buf[10] && event_vld[10] && ((!reg2hw.fatal_alert_en[10])))
             --------1-------    ------2------    ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T132
1	0	1	Covered	T123,T124,T125
1	1	0	Not Covered
1	1	1	Covered	T123,T124,T132

 LINE       214
 EXPRESSION (alert_en_buf[0] && event_vld[0] && reg2hw.fatal_alert_en[0])
             -------1-------    ------2-----    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T129,T130,T131
1	0	1	Not Covered
1	1	0	Covered	T123,T124,T125
1	1	1	Covered	T129,T130,T131

 LINE       225
 EXPRESSION (recov_event[0] & reg2hw.recov_alert[0].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T125
1	0	Covered	T123,T124,T125
1	1	Covered	T123,T124,T125

 LINE       225
 EXPRESSION (recov_event[1] & reg2hw.recov_alert[1].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T126
1	0	Covered	T123,T124,T126
1	1	Covered	T123,T124,T126

 LINE       225
 EXPRESSION (recov_event[2] & reg2hw.recov_alert[2].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T129
1	0	Covered	T123,T124,T129
1	1	Covered	T123,T124,T129

 LINE       225
 EXPRESSION (recov_event[3] & reg2hw.recov_alert[3].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T132
1	0	Covered	T123,T124,T132
1	1	Covered	T123,T124,T132

 LINE       225
 EXPRESSION (recov_event[4] & reg2hw.recov_alert[4].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T126
1	0	Covered	T123,T124,T126
1	1	Covered	T123,T124,T126

 LINE       225
 EXPRESSION (recov_event[5] & reg2hw.recov_alert[5].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T134
1	0	Covered	T123,T124,T134
1	1	Covered	T123,T124,T134

 LINE       225
 EXPRESSION (recov_event[6] & reg2hw.recov_alert[6].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T132
1	0	Covered	T123,T124,T132
1	1	Covered	T123,T124,T132

 LINE       225
 EXPRESSION (recov_event[7] & reg2hw.recov_alert[7].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T106
1	0	Covered	T123,T124,T106
1	1	Covered	T123,T124,T106

 LINE       225
 EXPRESSION (recov_event[8] & reg2hw.recov_alert[8].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T106
1	0	Covered	T123,T124,T106
1	1	Covered	T123,T124,T106

 LINE       225
 EXPRESSION (recov_event[9] & reg2hw.recov_alert[9].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T132
1	0	Covered	T123,T124,T132
1	1	Covered	T123,T124,T132

 LINE       225
 EXPRESSION (recov_event[10] & reg2hw.recov_alert[10].q)
             -------1-------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T123,T124,T132
1	0	Covered	T123,T124,T132
1	1	Covered	T123,T124,T132

 LINE       242
 EXPRESSION (alert_event_p[i] & event_clr[i])
             --------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T123,T124,T125
1	1	Covered	T123,T124,T125

 LINE       243
 SUB-EXPRESSION (((~alert_event_n[i])) & event_clr[i])
                 ----------1----------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T123,T124,T125
1	1	Covered	T123,T124,T125

 LINE       258
 EXPRESSION (reg2hw.alert_test.recov_alert.qe & reg2hw.alert_test.recov_alert.q)
             ----------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T56,T57
1	1	Covered	T55,T56,T57

 LINE       260
 EXPRESSION (reg2hw.alert_test.fatal_alert.qe & reg2hw.alert_test.fatal_alert.q)
             ----------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T56,T57
1	1	Covered	T55,T56,T57

 LINE       311
 EXPRESSION (((|(async_alert_event_p & alert_en_buf))) | ((~&(async_alert_event_n | (~alert_en_buf)))) | ((|reg2hw.recov_alert)))
             --------------------1--------------------   ----------------------2----------------------   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T123,T124,T125
0	1	0	Not Covered
1	0	0	Not Covered

---

Toggle Coverage for Module : sensor_ctrl

	Total	Covered	Percent
Totals	108	92	85.19
Total Bits	456	416	91.23
Total Bits 0->1	228	208	91.23
Total Bits 1->0	228	208	91.23

Ports	108	92	85.19
Port Bits	456	416	91.23
Port Bits 0->1	228	208	91.23
Port Bits 1->0	228	208	91.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T65,*T73,*T74	Yes	T65,T73,T74	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T123,T146,T124	Yes	T123,T146,T124	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T123,T146,T124	Yes	T123,T146,T124	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T1,*T3,*T34	Yes	T1,T2,T3	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T34	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_alert_i.alerts[0].n	Yes	Yes	T123,T124,T125	Yes	T125,T47,T48	INPUT
ast_alert_i.alerts[0].p	Yes	Yes	T125,T47,T48	Yes	T123,T124,T125	INPUT
ast_alert_i.alerts[1].n	Yes	Yes	T123,T124,T126	Yes	T126	INPUT
ast_alert_i.alerts[1].p	Yes	Yes	T126	Yes	T123,T124,T126	INPUT
ast_alert_i.alerts[2].n	Yes	Yes	T123,T124,T129	Yes	T129,T130,T131	INPUT
ast_alert_i.alerts[2].p	Yes	Yes	T129,T130,T131	Yes	T123,T124,T129	INPUT
ast_alert_i.alerts[3].n	No	Yes	T123,T124,T132	No		INPUT
ast_alert_i.alerts[3].p	No	No		Yes	T123,T124,T132	INPUT
ast_alert_i.alerts[4].n	Yes	Yes	T123,T124,T126	Yes	T126,T129,T130	INPUT
ast_alert_i.alerts[4].p	Yes	Yes	T126,T129,T130	Yes	T123,T124,T126	INPUT
ast_alert_i.alerts[5].n	Yes	Yes	T123,T124,T134	Yes	T134	INPUT
ast_alert_i.alerts[5].p	Yes	Yes	T134	Yes	T123,T124,T134	INPUT
ast_alert_i.alerts[6].n	No	Yes	T123,T124,T132	No		INPUT
ast_alert_i.alerts[6].p	No	No		Yes	T123,T124,T132	INPUT
ast_alert_i.alerts[7].n	Yes	Yes	T123,T124,T106	Yes	T106,T108	INPUT
ast_alert_i.alerts[7].p	Yes	Yes	T106,T108	Yes	T123,T124,T106	INPUT
ast_alert_i.alerts[8].n	Yes	Yes	T123,T124,T106	Yes	T106,T108	INPUT
ast_alert_i.alerts[8].p	Yes	Yes	T106,T108	Yes	T123,T124,T106	INPUT
ast_alert_i.alerts[9].n	No	Yes	T123,T124,T132	No		INPUT
ast_alert_i.alerts[9].p	No	No		Yes	T123,T124,T132	INPUT
ast_alert_i.alerts[10].n	No	Yes	T123,T124,T132	No		INPUT
ast_alert_i.alerts[10].p	No	No		Yes	T123,T124,T132	INPUT
ast_alert_o.alerts_trig[0].n	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
ast_alert_o.alerts_trig[0].p	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
ast_alert_o.alerts_trig[1].n	Yes	Yes	T123,T124,T126	Yes	T123,T124,T126	OUTPUT
ast_alert_o.alerts_trig[1].p	Yes	Yes	T123,T124,T126	Yes	T123,T124,T126	OUTPUT
ast_alert_o.alerts_trig[2].n	Yes	Yes	T123,T124,T129	Yes	T123,T124,T129	OUTPUT
ast_alert_o.alerts_trig[2].p	Yes	Yes	T123,T124,T129	Yes	T123,T124,T129	OUTPUT
ast_alert_o.alerts_trig[3].n	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_trig[3].p	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_trig[4].n	Yes	Yes	T123,T124,T126	Yes	T123,T124,T126	OUTPUT
ast_alert_o.alerts_trig[4].p	Yes	Yes	T123,T124,T126	Yes	T123,T124,T126	OUTPUT
ast_alert_o.alerts_trig[5].n	Yes	Yes	T123,T124,T134	Yes	T123,T124,T134	OUTPUT
ast_alert_o.alerts_trig[5].p	Yes	Yes	T123,T124,T134	Yes	T123,T124,T134	OUTPUT
ast_alert_o.alerts_trig[6].n	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_trig[6].p	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_trig[7].n	Yes	Yes	T123,T124,T106	Yes	T123,T124,T106	OUTPUT
ast_alert_o.alerts_trig[7].p	Yes	Yes	T123,T124,T106	Yes	T123,T124,T106	OUTPUT
ast_alert_o.alerts_trig[8].n	Yes	Yes	T123,T124,T106	Yes	T123,T124,T106	OUTPUT
ast_alert_o.alerts_trig[8].p	Yes	Yes	T123,T124,T106	Yes	T123,T124,T106	OUTPUT
ast_alert_o.alerts_trig[9].n	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_trig[9].p	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_trig[10].n	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_trig[10].p	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_ack[0].n	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
ast_alert_o.alerts_ack[0].p	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT
ast_alert_o.alerts_ack[1].n	Yes	Yes	T123,T124,T126	Yes	T123,T124,T126	OUTPUT
ast_alert_o.alerts_ack[1].p	Yes	Yes	T123,T124,T126	Yes	T123,T124,T126	OUTPUT
ast_alert_o.alerts_ack[2].n	Yes	Yes	T123,T124,T129	Yes	T123,T124,T129	OUTPUT
ast_alert_o.alerts_ack[2].p	Yes	Yes	T123,T124,T129	Yes	T123,T124,T129	OUTPUT
ast_alert_o.alerts_ack[3].n	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_ack[3].p	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_ack[4].n	Yes	Yes	T123,T124,T126	Yes	T123,T124,T126	OUTPUT
ast_alert_o.alerts_ack[4].p	Yes	Yes	T123,T124,T126	Yes	T123,T124,T126	OUTPUT
ast_alert_o.alerts_ack[5].n	Yes	Yes	T123,T124,T134	Yes	T123,T124,T134	OUTPUT
ast_alert_o.alerts_ack[5].p	Yes	Yes	T123,T124,T134	Yes	T123,T124,T134	OUTPUT
ast_alert_o.alerts_ack[6].n	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_ack[6].p	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_ack[7].n	Yes	Yes	T123,T124,T106	Yes	T123,T124,T106	OUTPUT
ast_alert_o.alerts_ack[7].p	Yes	Yes	T123,T124,T106	Yes	T123,T124,T106	OUTPUT
ast_alert_o.alerts_ack[8].n	Yes	Yes	T123,T124,T106	Yes	T123,T124,T106	OUTPUT
ast_alert_o.alerts_ack[8].p	Yes	Yes	T123,T124,T106	Yes	T123,T124,T106	OUTPUT
ast_alert_o.alerts_ack[9].n	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_ack[9].p	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_ack[10].n	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_alert_o.alerts_ack[10].p	Yes	Yes	T123,T124,T132	Yes	T123,T124,T132	OUTPUT
ast_status_i.io_pok[1:0]	Yes	Yes	T96,T137,T138	Yes	T1,T2,T3	INPUT
ast2pinmux_i[8:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_init_done_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T34	INPUT
cio_ast_debug_out_o[8:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ast_debug_out_en_o[8:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_io_status_change_o	Yes	Yes	T146,T147,T322	Yes	T146,T147,T322	OUTPUT
intr_init_status_change_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T123,T124	Yes	T59,T123,T124	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T59,T79,T80	Yes	T59,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T59,T79,T80	Yes	T59,T79,T80	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T320,T55,T126	Yes	T320,T55,T126	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T79,T150,T80	Yes	T79,T150,T80	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T79,T150,T80	Yes	T79,T150,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T123,T124	Yes	T59,T123,T124	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T320,T55,T126	Yes	T320,T55,T126	OUTPUT
wkup_req_o	Yes	Yes	T123,T124,T125	Yes	T123,T124,T125	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sensor_ctrl

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	327	2	2	100.00
IF	338	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	327	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	338	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : sensor_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmRegWeOnehotCheck_A	91249881	6	0	0
NumAlertsMatch_A	871	871	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91249881	6	0	0
T41	32821	0	0	0
T122	226227	0	0	0
T143	102875	0	0	0
T146	49180	0	0	0
T171	48759	0	0	0
T181	141117	0	0	0
T225	24508	0	0	0
T320	59197	1	0	0
T337	0	1	0	0
T338	0	1	0	0
T343	0	1	0	0
T344	0	1	0	0
T345	0	1	0	0
T346	23641	0	0	0
T347	19401	0	0	0

NumAlertsMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871	871	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0