Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T162,T163,T276
0	1	Covered	T162,T163,T276
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T162,T163,T276
1	Covered	T162,T163,T276

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T162,T163,T276
1	Covered	T162,T163,T276

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T162,T163,T276
1	1	Covered	T162,T163,T276

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T162,T163,T276
1	0	Covered	T162,T163,T276
1	1	Covered	T162,T163,T276

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T162,T163,T276

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T162,T163,T276
0	Covered	T162,T163,T276

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T162,T163,T276
0	Covered	T162,T163,T276

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	737962676	722461574	0	0
CheckNGreaterZero_A	1742	1742	0	0
GntImpliesReady_A	737962676	5422	0	0
GntImpliesValid_A	737962676	5422	0	0
GrantKnown_A	737962676	722461574	0	0
IdxKnown_A	737962676	722461574	0	0
IndexIsCorrect_A	737962676	5422	0	0
NoReadyValidNoGrant_A	737962676	0	0	0
Priority_A	737962676	5422	0	0
ReadyAndValidImplyGrant_A	737962676	5422	0	0
ReqAndReadyImplyGrant_A	737962676	5422	0	0
ReqImpliesValid_A	737962676	5422	0	0
ValidKnown_A	737962676	722461574	0	0
gen_data_port_assertion.DataFlow_A	737962676	5422	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	722461574	0	0
T1	563110	562878	0	0
T2	320902	320792	0	0
T3	536200	535974	0	0
T16	198054	197938	0	0
T34	581378	581058	0	0
T44	71170	71060	0	0
T59	1038334	1038312	0	0
T82	84502	84386	0	0
T83	169804	169694	0	0
T84	205278	205176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742	1742	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T16	2	2	0	0
T34	2	2	0	0
T44	2	2	0	0
T59	2	2	0	0
T82	2	2	0	0
T83	2	2	0	0
T84	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	5422	0	0
T35	182840	0	0	0
T162	166282	1804	0	0
T163	0	1798	0	0
T184	996858	0	0	0
T203	1889312	0	0	0
T226	167490	0	0	0
T276	0	1820	0	0
T278	433926	0	0	0
T279	596344	0	0	0
T280	429156	0	0	0
T281	1301158	0	0	0
T282	123516	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	5422	0	0
T35	182840	0	0	0
T162	166282	1804	0	0
T163	0	1798	0	0
T184	996858	0	0	0
T203	1889312	0	0	0
T226	167490	0	0	0
T276	0	1820	0	0
T278	433926	0	0	0
T279	596344	0	0	0
T280	429156	0	0	0
T281	1301158	0	0	0
T282	123516	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	722461574	0	0
T1	563110	562878	0	0
T2	320902	320792	0	0
T3	536200	535974	0	0
T16	198054	197938	0	0
T34	581378	581058	0	0
T44	71170	71060	0	0
T59	1038334	1038312	0	0
T82	84502	84386	0	0
T83	169804	169694	0	0
T84	205278	205176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	722461574	0	0
T1	563110	562878	0	0
T2	320902	320792	0	0
T3	536200	535974	0	0
T16	198054	197938	0	0
T34	581378	581058	0	0
T44	71170	71060	0	0
T59	1038334	1038312	0	0
T82	84502	84386	0	0
T83	169804	169694	0	0
T84	205278	205176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	5422	0	0
T35	182840	0	0	0
T162	166282	1804	0	0
T163	0	1798	0	0
T184	996858	0	0	0
T203	1889312	0	0	0
T226	167490	0	0	0
T276	0	1820	0	0
T278	433926	0	0	0
T279	596344	0	0	0
T280	429156	0	0	0
T281	1301158	0	0	0
T282	123516	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	5422	0	0
T35	182840	0	0	0
T162	166282	1804	0	0
T163	0	1798	0	0
T184	996858	0	0	0
T203	1889312	0	0	0
T226	167490	0	0	0
T276	0	1820	0	0
T278	433926	0	0	0
T279	596344	0	0	0
T280	429156	0	0	0
T281	1301158	0	0	0
T282	123516	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	5422	0	0
T35	182840	0	0	0
T162	166282	1804	0	0
T163	0	1798	0	0
T184	996858	0	0	0
T203	1889312	0	0	0
T226	167490	0	0	0
T276	0	1820	0	0
T278	433926	0	0	0
T279	596344	0	0	0
T280	429156	0	0	0
T281	1301158	0	0	0
T282	123516	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	5422	0	0
T35	182840	0	0	0
T162	166282	1804	0	0
T163	0	1798	0	0
T184	996858	0	0	0
T203	1889312	0	0	0
T226	167490	0	0	0
T276	0	1820	0	0
T278	433926	0	0	0
T279	596344	0	0	0
T280	429156	0	0	0
T281	1301158	0	0	0
T282	123516	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	5422	0	0
T35	182840	0	0	0
T162	166282	1804	0	0
T163	0	1798	0	0
T184	996858	0	0	0
T203	1889312	0	0	0
T226	167490	0	0	0
T276	0	1820	0	0
T278	433926	0	0	0
T279	596344	0	0	0
T280	429156	0	0	0
T281	1301158	0	0	0
T282	123516	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	722461574	0	0
T1	563110	562878	0	0
T2	320902	320792	0	0
T3	536200	535974	0	0
T16	198054	197938	0	0
T34	581378	581058	0	0
T44	71170	71060	0	0
T59	1038334	1038312	0	0
T82	84502	84386	0	0
T83	169804	169694	0	0
T84	205278	205176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737962676	5422	0	0
T35	182840	0	0	0
T162	166282	1804	0	0
T163	0	1798	0	0
T184	996858	0	0	0
T203	1889312	0	0	0
T226	167490	0	0	0
T276	0	1820	0	0
T278	433926	0	0	0
T279	596344	0	0	0
T280	429156	0	0	0
T281	1301158	0	0	0
T282	123516	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T162,T163,T276
0	1	Covered	T162,T163,T276
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T162,T163,T276
1	Covered	T162,T163,T276

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T162,T163,T276
1	Covered	T162,T163,T276

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T162,T163,T276
1	1	Covered	T162,T163,T276

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T162,T163,T276
1	0	Covered	T162,T163,T276
1	1	Covered	T162,T163,T276

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T162,T163,T276

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T162,T163,T276
0	Covered	T162,T163,T276

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T162,T163,T276
0	Covered	T162,T163,T276

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	368981338	361230787	0	0
CheckNGreaterZero_A	871	871	0	0
GntImpliesReady_A	368981338	4384	0	0
GntImpliesValid_A	368981338	4384	0	0
GrantKnown_A	368981338	361230787	0	0
IdxKnown_A	368981338	361230787	0	0
IndexIsCorrect_A	368981338	4384	0	0
NoReadyValidNoGrant_A	368981338	0	0	0
Priority_A	368981338	4384	0	0
ReadyAndValidImplyGrant_A	368981338	4384	0	0
ReqAndReadyImplyGrant_A	368981338	4384	0	0
ReqImpliesValid_A	368981338	4384	0	0
ValidKnown_A	368981338	361230787	0	0
gen_data_port_assertion.DataFlow_A	368981338	4384	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	361230787	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871	871	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	4384	0	0
T35	91420	0	0	0
T162	83141	1458	0	0
T163	0	1452	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	1474	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	4384	0	0
T35	91420	0	0	0
T162	83141	1458	0	0
T163	0	1452	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	1474	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	361230787	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	361230787	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	4384	0	0
T35	91420	0	0	0
T162	83141	1458	0	0
T163	0	1452	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	1474	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	4384	0	0
T35	91420	0	0	0
T162	83141	1458	0	0
T163	0	1452	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	1474	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	4384	0	0
T35	91420	0	0	0
T162	83141	1458	0	0
T163	0	1452	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	1474	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	4384	0	0
T35	91420	0	0	0
T162	83141	1458	0	0
T163	0	1452	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	1474	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	4384	0	0
T35	91420	0	0	0
T162	83141	1458	0	0
T163	0	1452	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	1474	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	361230787	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	4384	0	0
T35	91420	0	0	0
T162	83141	1458	0	0
T163	0	1452	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	1474	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T162,T163,T276
0	1	Covered	T162,T163,T276
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T162,T163,T276
1	Covered	T162,T163,T276

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T162,T163,T276
1	Covered	T162,T163,T276

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T162,T163,T276
1	1	Covered	T162,T163,T276

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T162,T163,T276
1	0	Covered	T162,T163,T276
1	1	Covered	T162,T163,T276

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T162,T163,T276

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T162,T163,T276
0	Covered	T162,T163,T276

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T162,T163,T276
0	Covered	T162,T163,T276

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	368981338	361230787	0	0
CheckNGreaterZero_A	871	871	0	0
GntImpliesReady_A	368981338	1038	0	0
GntImpliesValid_A	368981338	1038	0	0
GrantKnown_A	368981338	361230787	0	0
IdxKnown_A	368981338	361230787	0	0
IndexIsCorrect_A	368981338	1038	0	0
NoReadyValidNoGrant_A	368981338	0	0	0
Priority_A	368981338	1038	0	0
ReadyAndValidImplyGrant_A	368981338	1038	0	0
ReqAndReadyImplyGrant_A	368981338	1038	0	0
ReqImpliesValid_A	368981338	1038	0	0
ValidKnown_A	368981338	361230787	0	0
gen_data_port_assertion.DataFlow_A	368981338	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	361230787	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	871	871	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T59	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	1038	0	0
T35	91420	0	0	0
T162	83141	346	0	0
T163	0	346	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	346	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	1038	0	0
T35	91420	0	0	0
T162	83141	346	0	0
T163	0	346	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	346	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	361230787	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	361230787	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	1038	0	0
T35	91420	0	0	0
T162	83141	346	0	0
T163	0	346	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	346	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	1038	0	0
T35	91420	0	0	0
T162	83141	346	0	0
T163	0	346	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	346	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	1038	0	0
T35	91420	0	0	0
T162	83141	346	0	0
T163	0	346	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	346	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	1038	0	0
T35	91420	0	0	0
T162	83141	346	0	0
T163	0	346	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	346	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	1038	0	0
T35	91420	0	0	0
T162	83141	346	0	0
T163	0	346	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	346	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	361230787	0	0
T1	281555	281439	0	0
T2	160451	160396	0	0
T3	268100	267987	0	0
T16	99027	98969	0	0
T34	290689	290529	0	0
T44	35585	35530	0	0
T59	519167	519156	0	0
T82	42251	42193	0	0
T83	84902	84847	0	0
T84	102639	102588	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368981338	1038	0	0
T35	91420	0	0	0
T162	83141	346	0	0
T163	0	346	0	0
T184	498429	0	0	0
T203	944656	0	0	0
T226	83745	0	0	0
T276	0	346	0	0
T278	216963	0	0	0
T279	298172	0	0	0
T280	214578	0	0	0
T281	650579	0	0	0
T282	61758	0	0	0