Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3646661	1			T71	1642		T72	125		T73	565
values[2]	733240	1			T71	411		T72	68		T73	137
values[3]	102562	1			T71	1		T146	248		T222	227
values[4]	53291	1			T146	129		T222	103		T510	88
values[5]	37014	1			T146	64		T222	36		T510	92
values[6]	27527	1			T146	60		T222	36		T510	84
values[7]	22237	1			T146	36		T222	31		T510	83
values[8]	19107	1			T146	56		T222	29		T510	99
values[9]	16630	1			T146	39		T222	32		T510	100
values[10]	14517	1			T146	61		T222	40		T510	98
values[11]	13045	1			T146	37		T222	27		T510	80
values[12]	12307	1			T146	66		T222	18		T510	102
values[13]	11554	1			T146	66		T222	12		T510	92
values[14]	10987	1			T146	55		T222	11		T510	100
values[15]	10777	1			T146	40		T222	30		T510	92
values[16]	10615	1			T146	31		T222	10		T510	83
values[17]	10239	1			T146	15		T222	1		T510	89
values[18]	9688	1			T146	19		T510	99		T514	8
values[19]	9231	1			T146	16		T510	92		T514	6
values[20]	8835	1			T146	14		T510	84		T514	4
values[21]	8396	1			T146	10		T510	62		T514	8
values[22]	8010	1			T146	7		T510	82		T514	4
values[23]	7766	1			T146	10		T510	88		T514	4
values[24]	7700	1			T146	9		T510	90		T514	4
values[25]	7223	1			T146	9		T510	86		T514	3
values[26]	7085	1			T146	6		T510	61		T514	2
values[27]	6807	1			T146	7		T510	81		T514	2
values[28]	6504	1			T146	19		T510	68		T514	2
values[29]	6103	1			T146	11		T510	62		T514	3
values[30]	5736	1			T146	5		T510	50		T514	3
values[31]	5685	1			T146	9		T510	39		T514	6
values[32]	5033	1			T146	4		T510	37		T514	5
values[33]	4689	1			T146	11		T510	35		T514	2
values[34]	4495	1			T146	18		T510	52		T514	2
values[35]	4213	1			T146	25		T510	37		T514	3
values[36]	3969	1			T146	29		T510	34		T514	7
values[37]	3854	1			T146	15		T510	21		T514	2
values[38]	3665	1			T146	9		T510	19		T514	2
values[39]	3668	1			T146	8		T510	12		T514	4
values[40]	3415	1			T146	8		T510	15		T514	9
values[41]	3243	1			T146	10		T510	11		T514	6
values[42]	3199	1			T146	13		T510	13		T514	5
values[43]	3115	1			T146	12		T510	14		T514	4
values[44]	3016	1			T146	10		T510	15		T514	5
values[45]	3063	1			T146	13		T510	13		T514	6
values[46]	2955	1			T146	7		T510	9		T514	3
values[47]	2887	1			T146	1		T510	11		T514	2
values[48]	2938	1			T146	2		T510	14		T514	5
values[49]	2752	1			T146	1		T510	9		T514	3
values[50]	2712	1			T146	5		T510	12		T514	3
values[51]	2651	1			T146	3		T510	10		T514	3
values[52]	2560	1			T146	1		T510	9		T514	3
values[53]	2582	1			T146	1		T510	11		T514	3
values[54]	2537	1			T146	1		T510	16		T514	2
values[55]	2616	1			T146	3		T510	6		T514	2
values[56]	2498	1			T146	1		T510	2		T514	5
values[57]	2586	1			T146	2		T510	5		T514	5
values[58]	2447	1			T146	1		T510	3		T514	3
values[59]	2447	1			T146	1		T510	3		T514	2
values[60]	2471	1			T146	2		T510	3		T514	6
values[61]	2584	1			T146	3		T510	1		T514	5
values[62]	3889	1			T146	3		T510	3		T514	7
values[63]	13868	1			T146	11		T510	8		T514	27
values[64]	229214	1			T146	50		T510	128		T514	108

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4684303	1			T71	1858		T72	122		T73	606
values[2]	771670	1			T71	490		T72	33		T73	142
values[3]	77177	1			T71	4		T73	5		T146	218
values[4]	14233	1			T73	1		T146	17		T223	1
values[5]	5889	1			T146	5		T510	1		T504	7
values[6]	3765	1			T146	6		T510	2		T504	2
values[7]	2853	1			T146	8		T510	1		T514	15
values[8]	2435	1			T146	3		T510	1		T514	3
values[9]	1974	1			T146	11		T510	3		T514	4
values[10]	1758	1			T146	29		T510	2		T514	5
values[11]	1597	1			T146	21		T510	1		T514	5
values[12]	1445	1			T146	16		T510	1		T514	20
values[13]	1484	1			T146	11		T510	1		T514	25
values[14]	1385	1			T146	10		T510	3		T514	15
values[15]	1275	1			T146	5		T510	2		T514	23
values[16]	1104	1			T146	3		T510	2		T514	4
values[17]	1076	1			T146	2		T510	1		T514	1
values[18]	1091	1			T146	4		T510	1		T514	1
values[19]	917	1			T146	5		T510	1		T514	2
values[20]	844	1			T146	14		T510	1		T514	1
values[21]	809	1			T146	5		T510	1		T514	1
values[22]	753	1			T146	3		T510	1		T514	1
values[23]	721	1			T146	7		T510	1		T514	1
values[24]	680	1			T146	7		T510	1		T514	4
values[25]	706	1			T146	6		T510	2		T514	9
values[26]	731	1			T146	1		T510	2		T514	3
values[27]	692	1			T146	2		T510	7		T514	1
values[28]	708	1			T146	1		T510	4		T514	2
values[29]	669	1			T146	1		T510	2		T514	3
values[30]	636	1			T146	2		T510	1		T514	1
values[31]	613	1			T146	2		T510	2		T514	6
values[32]	605	1			T146	1		T510	2		T514	1
values[33]	602	1			T146	2		T510	1		T514	4
values[34]	611	1			T146	5		T510	1		T514	3
values[35]	581	1			T146	4		T510	1		T514	3
values[36]	523	1			T146	7		T510	1		T514	2
values[37]	488	1			T146	1		T510	1		T514	2
values[38]	474	1			T146	3		T510	1		T514	1
values[39]	524	1			T146	7		T510	2		T514	2
values[40]	564	1			T146	7		T510	2		T514	2
values[41]	546	1			T146	7		T510	2		T514	1
values[42]	453	1			T146	2		T510	1		T514	3
values[43]	447	1			T146	1		T510	5		T514	6
values[44]	435	1			T146	1		T510	2		T514	1
values[45]	471	1			T510	2		T514	3		T437	2
values[46]	425	1			T510	2		T514	2		T437	2
values[47]	427	1			T510	1		T514	1		T437	2
values[48]	446	1			T510	1		T514	2		T437	2
values[49]	456	1			T510	1		T514	4		T437	1
values[50]	465	1			T510	1		T514	1		T437	4
values[51]	457	1			T510	2		T514	3		T437	4
values[52]	467	1			T510	1		T514	4		T437	1
values[53]	435	1			T510	1		T514	3		T437	2
values[54]	449	1			T510	5		T514	1		T437	1
values[55]	436	1			T510	4		T514	1		T815	3
values[56]	445	1			T510	1		T514	1		T815	3
values[57]	433	1			T510	2		T514	1		T815	4
values[58]	431	1			T510	1		T514	2		T815	2
values[59]	412	1			T510	1		T514	2		T815	3
values[60]	407	1			T510	1		T514	3		T815	3
values[61]	433	1			T510	1		T514	1		T815	2
values[62]	725	1			T510	2		T514	5		T815	2
values[63]	2977	1			T510	6		T514	7		T815	10
values[64]	30799	1			T510	90		T514	11		T815	98

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	596610	1			T71	16		T72	1		T73	5
values[2]	2560365	1			T71	1832		T72	100		T73	516
values[3]	1164840	1			T71	542		T72	44		T73	143
values[4]	146626	1			T71	2		T146	431		T222	204
values[5]	74480	1			T146	250		T222	128		T510	96
values[6]	48042	1			T146	173		T222	81		T510	93
values[7]	34785	1			T146	115		T222	67		T510	67
values[8]	27402	1			T146	75		T222	51		T510	76
values[9]	22387	1			T146	58		T222	33		T510	82
values[10]	19766	1			T146	77		T222	25		T510	85
values[11]	17695	1			T146	83		T222	35		T510	78
values[12]	16016	1			T146	95		T222	45		T510	92
values[13]	14796	1			T146	108		T222	26		T510	117
values[14]	14089	1			T146	78		T222	32		T510	79
values[15]	13376	1			T146	79		T222	27		T510	79
values[16]	12691	1			T146	74		T222	22		T510	78
values[17]	11874	1			T146	68		T222	15		T510	92
values[18]	11449	1			T146	104		T222	7		T510	66
values[19]	10681	1			T146	77		T222	1		T510	97
values[20]	10259	1			T146	59		T510	94		T514	2
values[21]	10127	1			T146	76		T510	75		T514	3
values[22]	9675	1			T146	71		T510	106		T514	2
values[23]	9331	1			T146	72		T510	89		T514	6
values[24]	9122	1			T146	73		T510	61		T514	5
values[25]	8562	1			T146	55		T510	77		T514	4
values[26]	8095	1			T146	49		T510	68		T514	5
values[27]	7913	1			T146	33		T510	82		T514	11
values[28]	7522	1			T146	32		T510	75		T514	5
values[29]	6873	1			T146	36		T510	36		T514	5
values[30]	6334	1			T146	18		T510	54		T514	4
values[31]	6094	1			T146	13		T510	51		T514	3
values[32]	5531	1			T146	14		T510	36		T514	4
values[33]	5229	1			T146	14		T510	37		T514	6
values[34]	4657	1			T146	26		T510	27		T514	5
values[35]	4412	1			T146	21		T510	15		T514	6
values[36]	4216	1			T146	31		T510	17		T514	8
values[37]	3927	1			T146	16		T510	12		T514	4
values[38]	3716	1			T146	8		T510	9		T514	7
values[39]	3649	1			T146	9		T510	12		T514	3
values[40]	3520	1			T146	22		T510	7		T514	3
values[41]	3589	1			T146	31		T510	10		T514	5
values[42]	3479	1			T146	24		T510	13		T514	6
values[43]	3422	1			T146	12		T510	8		T514	7
values[44]	3431	1			T146	21		T510	11		T514	8
values[45]	3217	1			T146	18		T510	11		T514	5
values[46]	3211	1			T146	15		T510	12		T514	6
values[47]	3222	1			T146	13		T510	6		T514	8
values[48]	3142	1			T146	10		T510	11		T514	7
values[49]	3110	1			T146	7		T510	5		T514	2
values[50]	3093	1			T146	10		T510	5		T514	6
values[51]	2982	1			T146	5		T510	6		T514	5
values[52]	2956	1			T146	7		T510	1		T514	4
values[53]	2853	1			T146	4		T510	1		T514	4
values[54]	2874	1			T146	6		T510	2		T514	3
values[55]	2818	1			T146	7		T510	1		T514	3
values[56]	2804	1			T146	8		T510	2		T514	6
values[57]	2783	1			T146	6		T510	1		T514	9
values[58]	2728	1			T146	9		T510	2		T514	7
values[59]	2762	1			T146	16		T510	1		T514	11
values[60]	2791	1			T146	19		T510	5		T514	17
values[61]	2816	1			T146	7		T510	1		T514	6
values[62]	3821	1			T146	8		T510	1		T514	12
values[63]	17494	1			T146	27		T510	2		T514	50
values[64]	217766	1			T146	178		T510	109		T514	69