Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1835910	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

22319543

1

T1

18585

T2

374105

T3

16803

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15484641	1			T1	4570		T2	350233		T3	7947
values[0x0]	7322454	1			T1	14015		T2	23872		T3	8856
values[0x1]	1348358	1			T1	504		T2	44		T3	1408

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	617915	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23537538

1

T1

19089

T2

374149

T3

18211

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10920855	1			T1	9546		T2	187075		T3	9106
valid_sources[0x01]	10918864	1			T1	9543		T2	187074		T3	9105
valid_sources[0x02]	36922	1			T50	2		T393	1		T138	2950
valid_sources[0x03]	36727	1			T75	1		T138	2836		T139	93
valid_sources[0x04]	37476	1			T138	3125		T139	71		T140	180
valid_sources[0x05]	36443	1			T76	1		T393	3		T138	2876
valid_sources[0x06]	37919	1			T75	3		T393	2		T138	3081
valid_sources[0x07]	37809	1			T75	1		T502	2		T50	2
valid_sources[0x08]	37942	1			T50	1		T138	3134		T139	87
valid_sources[0x09]	37300	1			T76	1		T138	2932		T139	78
valid_sources[0x0a]	37971	1			T75	2		T76	3		T50	1
valid_sources[0x0b]	36950	1			T138	2993		T139	94		T140	191
valid_sources[0x0c]	37949	1			T76	2		T50	1		T393	3
valid_sources[0x0d]	36835	1			T75	3		T502	3		T50	1
valid_sources[0x0e]	37031	1			T75	1		T76	1		T393	1
valid_sources[0x0f]	37129	1			T76	1		T138	3101		T139	82
valid_sources[0x10]	36567	1			T138	2839		T139	85		T140	173
valid_sources[0x11]	36772	1			T75	1		T393	5		T138	2793
valid_sources[0x12]	37670	1			T75	1		T76	2		T50	1
valid_sources[0x13]	36734	1			T502	2		T50	2		T138	2749
valid_sources[0x14]	38302	1			T75	1		T502	9		T138	3061
valid_sources[0x15]	37194	1			T50	2		T138	2886		T139	109
valid_sources[0x16]	37224	1			T76	1		T393	1		T138	2901
valid_sources[0x17]	36245	1			T76	1		T138	2775		T139	68
valid_sources[0x18]	37684	1			T50	1		T138	3024		T139	106
valid_sources[0x19]	37218	1			T502	1		T50	1		T393	2
valid_sources[0x1a]	38311	1			T138	3089		T139	94		T140	162
valid_sources[0x1b]	38134	1			T75	1		T76	3		T50	1
valid_sources[0x1c]	37776	1			T75	1		T76	1		T50	2
valid_sources[0x1d]	36978	1			T75	1		T502	2		T393	1
valid_sources[0x1e]	36922	1			T50	1		T393	2		T138	2850
valid_sources[0x1f]	36858	1			T50	1		T138	3086		T139	56
valid_sources[0x20]	36839	1			T75	1		T138	3058		T139	85

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14791447

1

T1

4570

T2

350233

T3

7947

values[0x0]

all_enables

biggest_size

7278309

1

T1

14015

T2

23872

T3

8856

values[0x1]

all_enables

biggest_size

249787

1

T75

18

T48

15

T76

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2846499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

449944

1

T71

289

T72

30

T73

94

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1115126	1			T71	680		T72	52		T73	243
values[0x0]	1065529	1			T71	680		T72	69		T73	227
values[0x1]	1115788	1			T71	694		T72	72		T73	232

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2204107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1092336

1

T71

699

T72

63

T73

228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51440	1			T71	11		T72	6		T73	17
valid_sources[0x01]	51277	1			T71	22		T72	2		T73	8
valid_sources[0x02]	50740	1			T71	64		T72	2		T73	12
valid_sources[0x03]	51561	1			T71	65		T73	10		T146	174
valid_sources[0x04]	52294	1			T71	48		T72	2		T73	13
valid_sources[0x05]	50628	1			T71	36		T72	2		T73	10
valid_sources[0x06]	51480	1			T71	2		T72	2		T73	6
valid_sources[0x07]	52290	1			T71	28		T72	4		T73	16
valid_sources[0x08]	52069	1			T71	23		T72	3		T73	12
valid_sources[0x09]	51138	1			T71	30		T72	3		T73	9
valid_sources[0x0a]	51404	1			T71	11		T73	9		T146	152
valid_sources[0x0b]	52256	1			T71	39		T72	3		T73	12
valid_sources[0x0c]	52327	1			T71	24		T72	5		T73	12
valid_sources[0x0d]	51138	1			T71	32		T72	2		T73	10
valid_sources[0x0e]	51238	1			T71	34		T72	2		T73	10
valid_sources[0x0f]	51342	1			T71	15		T72	5		T73	9
valid_sources[0x10]	51049	1			T71	31		T72	2		T73	9
valid_sources[0x11]	51744	1			T71	46		T72	4		T73	9
valid_sources[0x12]	53509	1			T71	44		T72	2		T73	15
valid_sources[0x13]	51746	1			T71	19		T72	4		T73	11
valid_sources[0x14]	52315	1			T71	33		T72	1		T73	8
valid_sources[0x15]	51972	1			T71	16		T72	2		T73	9
valid_sources[0x16]	50869	1			T71	22		T72	4		T73	8
valid_sources[0x17]	52132	1			T71	21		T72	2		T73	12
valid_sources[0x18]	50904	1			T71	28		T72	2		T73	11
valid_sources[0x19]	50390	1			T71	29		T72	2		T73	8
valid_sources[0x1a]	51675	1			T71	66		T72	1		T73	10
valid_sources[0x1b]	51095	1			T71	24		T72	4		T73	11
valid_sources[0x1c]	51299	1			T71	20		T72	1		T73	19
valid_sources[0x1d]	50379	1			T71	71		T72	1		T73	10
valid_sources[0x1e]	52008	1			T71	48		T72	3		T73	15
valid_sources[0x1f]	51925	1			T71	25		T72	8		T73	8
valid_sources[0x20]	51955	1			T71	19		T72	4		T73	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47223

1

T71

29

T72

4

T73

14

values[0x0]

all_enables

biggest_size

355282

1

T71

232

T72

21

T73

67

values[0x1]

all_enables

biggest_size

47439

1

T71

28

T72

5

T73

13

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3031202	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

494056

1

T71

294

T72

19

T73

109

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1205138	1			T71	823		T72	45		T73	263
values[0x0]	1113152	1			T71	749		T72	48		T73	249
values[0x1]	1206968	1			T71	780		T72	62		T73	242

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2325634	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1199624

1

T71

768

T72

50

T73

279

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54545	1			T71	25		T72	2		T73	1
valid_sources[0x01]	56107	1			T71	44		T72	3		T146	202
valid_sources[0x02]	54440	1			T71	10		T72	4		T73	7
valid_sources[0x03]	55161	1			T71	18		T72	1		T73	17
valid_sources[0x04]	55388	1			T71	48		T72	2		T73	19
valid_sources[0x05]	55479	1			T71	12		T72	1		T73	13
valid_sources[0x06]	56036	1			T71	84		T72	4		T73	2
valid_sources[0x07]	55164	1			T71	31		T72	1		T73	3
valid_sources[0x08]	55523	1			T71	37		T72	1		T73	13
valid_sources[0x09]	54913	1			T71	41		T73	21		T146	215
valid_sources[0x0a]	55011	1			T71	36		T72	6		T73	15
valid_sources[0x0b]	56328	1			T71	30		T72	3		T73	4
valid_sources[0x0c]	55815	1			T71	20		T72	5		T73	9
valid_sources[0x0d]	55380	1			T71	26		T72	4		T73	27
valid_sources[0x0e]	54708	1			T71	42		T72	2		T73	12
valid_sources[0x0f]	54873	1			T71	75		T72	2		T146	147
valid_sources[0x10]	55699	1			T71	20		T73	36		T146	139
valid_sources[0x11]	56141	1			T71	13		T72	3		T146	241
valid_sources[0x12]	54430	1			T71	33		T72	4		T73	6
valid_sources[0x13]	54367	1			T71	63		T72	1		T73	34
valid_sources[0x14]	55798	1			T71	48		T146	146		T222	149
valid_sources[0x15]	55095	1			T71	44		T72	2		T73	3
valid_sources[0x16]	53749	1			T71	21		T72	3		T146	152
valid_sources[0x17]	54737	1			T71	61		T72	4		T73	25
valid_sources[0x18]	53946	1			T71	22		T72	2		T73	9
valid_sources[0x19]	54291	1			T71	36		T72	3		T73	13
valid_sources[0x1a]	54232	1			T71	53		T72	3		T73	4
valid_sources[0x1b]	55172	1			T71	19		T72	1		T73	1
valid_sources[0x1c]	55692	1			T71	25		T72	5		T73	62
valid_sources[0x1d]	54965	1			T71	26		T72	3		T73	16
valid_sources[0x1e]	55763	1			T71	34		T72	5		T73	24
valid_sources[0x1f]	53996	1			T71	49		T72	1		T73	2
valid_sources[0x20]	54865	1			T71	28		T72	3		T73	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51937

1

T71

31

T72

1

T73

7

values[0x0]

all_enables

biggest_size

390571

1

T71

241

T72

13

T73

91

values[0x1]

all_enables

biggest_size

51548

1

T71

22

T72

5

T73

11

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2868908	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

454490

1

T71

317

T72

26

T73

81

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1124960	1			T71	801		T72	49		T73	223
values[0x0]	1072692	1			T71	779		T72	47		T73	208
values[0x1]	1125746	1			T71	812		T72	49		T73	233

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2221285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1102113

1

T71

784

T72

56

T73

207

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51877	1			T71	48		T72	4		T73	3
valid_sources[0x01]	51921	1			T71	29		T72	4		T73	15
valid_sources[0x02]	52284	1			T71	36		T72	1		T73	7
valid_sources[0x03]	52754	1			T71	31		T72	3		T73	5
valid_sources[0x04]	51769	1			T71	44		T72	4		T73	18
valid_sources[0x05]	52144	1			T71	37		T72	2		T73	10
valid_sources[0x06]	51304	1			T71	40		T72	4		T73	13
valid_sources[0x07]	52482	1			T71	28		T73	5		T146	177
valid_sources[0x08]	52779	1			T71	36		T73	13		T146	137
valid_sources[0x09]	51124	1			T71	41		T72	3		T73	13
valid_sources[0x0a]	51700	1			T71	37		T72	2		T73	5
valid_sources[0x0b]	52701	1			T71	38		T72	1		T73	22
valid_sources[0x0c]	53083	1			T71	37		T72	4		T146	172
valid_sources[0x0d]	50819	1			T71	26		T72	2		T73	7
valid_sources[0x0e]	52056	1			T71	44		T72	1		T146	114
valid_sources[0x0f]	52283	1			T71	24		T72	2		T73	10
valid_sources[0x10]	52056	1			T71	34		T72	3		T73	11
valid_sources[0x11]	51859	1			T71	33		T72	3		T73	16
valid_sources[0x12]	52131	1			T71	45		T72	2		T73	13
valid_sources[0x13]	51488	1			T71	37		T73	24		T146	161
valid_sources[0x14]	51951	1			T71	45		T72	3		T73	10
valid_sources[0x15]	51640	1			T71	61		T72	3		T73	25
valid_sources[0x16]	52053	1			T71	42		T72	3		T73	21
valid_sources[0x17]	51759	1			T71	38		T72	2		T73	22
valid_sources[0x18]	50888	1			T71	27		T72	2		T73	12
valid_sources[0x19]	50955	1			T71	32		T72	1		T73	4
valid_sources[0x1a]	51834	1			T71	45		T73	31		T146	142
valid_sources[0x1b]	51458	1			T71	39		T72	1		T73	38
valid_sources[0x1c]	51554	1			T71	35		T72	2		T73	4
valid_sources[0x1d]	52207	1			T71	39		T72	3		T73	4
valid_sources[0x1e]	52212	1			T71	28		T72	2		T73	28
valid_sources[0x1f]	51686	1			T71	54		T72	8		T73	1
valid_sources[0x20]	51253	1			T71	33		T72	1		T73	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48034

1

T71

28

T72

5

T73

10

values[0x0]

all_enables

biggest_size

358627

1

T71

265

T72

19

T73

57

values[0x1]

all_enables

biggest_size

47829

1

T71

24

T72

2

T73

14