Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : ibex_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.16 94.16

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core 96.51 96.51


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.51 96.51


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.51 96.51


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.79 96.47 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : ibex_top
TotalCoveredPercent
Totals 40 33 82.50
Total Bits 822 774 94.16
Total Bits 0->1 411 387 94.16
Total Bits 1->0 411 387 94.16

Ports 40 33 82.50
Port Bits 822 774 94.16
Port Bits 0->1 411 387 94.16
Port Bits 1->0 411 387 94.16

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
test_en_i No No No INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
instr_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
instr_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
instr_addr_o[16:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
instr_addr_o[27:17] No No No OUTPUT
instr_addr_o[29:28] Yes Yes *T5,*T212,*T172 Yes T5,T212,T172 OUTPUT
instr_addr_o[30] No No No OUTPUT
instr_addr_o[31] Yes Yes T174,T270,T272 Yes T174,T270,T272 OUTPUT
instr_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_err_i Yes Yes T60,T5,T193 Yes T60,T5,T193 INPUT
data_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_we_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_be_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
data_addr_o[31:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_intg_o[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_err_i Yes Yes T3,T60,T61 Yes T3,T60,T61 INPUT
irq_software_i Yes Yes T104,T227,T228 Yes T104,T227,T228 INPUT
irq_timer_i Yes Yes T229,T147,T148 Yes T229,T147,T148 INPUT
irq_external_i Yes Yes T3,T55,T59 Yes T3,T55,T59 INPUT
irq_fast_i[14:0] Unreachable Unreachable Unreachable INPUT
irq_nm_i Yes Yes T3,T60,T230 Yes T3,T60,T230 INPUT
scramble_key_valid_i Yes Yes T171,T173,T174 Yes T171,T173,T174 INPUT
scramble_key_i[127:0] Yes Yes T1,T3,T55 Yes T1,T3,T82 INPUT
scramble_nonce_i[63:0] Yes Yes T1,T3,T59 Yes T1,T3,T55 INPUT
scramble_req_o Yes Yes T5,T171,T172 Yes T5,T171,T172 OUTPUT
debug_req_i Yes Yes T74,T232,T233 Yes T74,T232,T233 INPUT
crash_dump_o.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
double_fault_seen_o Yes Yes T213,T214,T215 Yes T213,T214,T215 OUTPUT
fetch_enable_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_minor_o No No No OUTPUT
alert_major_internal_o Yes Yes T351 Yes T351,T352,T353 OUTPUT
alert_major_bus_o Yes Yes T82,T85,T212 Yes T82,T85,T212 OUTPUT
core_sleep_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core
TotalCoveredPercent
Totals 36 33 91.67
Total Bits 802 774 96.51
Total Bits 0->1 401 387 96.51
Total Bits 1->0 401 387 96.51

Ports 36 33 91.67
Port Bits 802 774 96.51
Port Bits 0->1 401 387 96.51
Port Bits 1->0 401 387 96.51

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
test_en_i No No No INPUT
ram_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
instr_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
instr_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
instr_addr_o[16:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
instr_addr_o[27:17] No No No OUTPUT
instr_addr_o[29:28] Yes Yes *T5,*T212,*T172 Yes T5,T212,T172 OUTPUT
instr_addr_o[30] No No No OUTPUT
instr_addr_o[31] Yes Yes T174,T270,T272 Yes T174,T270,T272 OUTPUT
instr_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
instr_err_i Yes Yes T60,T5,T193 Yes T60,T5,T193 INPUT
data_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_gnt_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rvalid_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_we_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_be_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_addr_o[1:0] Unreachable Unreachable Unreachable OUTPUT
data_addr_o[31:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_wdata_intg_o[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
data_rdata_i[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_rdata_intg_i[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_err_i Yes Yes T3,T60,T61 Yes T3,T60,T61 INPUT
irq_software_i Yes Yes T104,T227,T228 Yes T104,T227,T228 INPUT
irq_timer_i Yes Yes T229,T147,T148 Yes T229,T147,T148 INPUT
irq_external_i Yes Yes T3,T55,T59 Yes T3,T55,T59 INPUT
irq_fast_i[14:0] Unreachable Unreachable Unreachable INPUT
irq_nm_i Yes Yes T3,T60,T230 Yes T3,T60,T230 INPUT
scramble_key_valid_i Yes Yes T171,T173,T174 Yes T171,T173,T174 INPUT
scramble_key_i[127:0] Yes Yes T1,T3,T55 Yes T1,T3,T82 INPUT
scramble_nonce_i[63:0] Yes Yes T1,T3,T59 Yes T1,T3,T55 INPUT
scramble_req_o Yes Yes T5,T171,T172 Yes T5,T171,T172 OUTPUT
debug_req_i Yes Yes T74,T232,T233 Yes T74,T232,T233 INPUT
crash_dump_o.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
double_fault_seen_o Yes Yes T213,T214,T215 Yes T213,T214,T215 OUTPUT
fetch_enable_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_minor_o No No No OUTPUT
alert_major_internal_o Yes Yes T351 Yes T351,T352,T353 OUTPUT
alert_major_bus_o Yes Yes T82,T85,T212 Yes T82,T85,T212 OUTPUT
core_sleep_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%