Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376859819	39700469	0	0
DepthKnown_A	376859819	376766100	0	0
RvalidKnown_A	376859819	376766100	0	0
WreadyKnown_A	376859819	376766100	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	39700469	0	0
T1	522530	46277	0	0
T2	542145	354793	0	0
T3	272356	35684	0	0
T55	151239	24446	0	0
T59	155970	25260	0	0
T81	219720	22398	0	0
T82	224587	26776	0	0
T83	127168	21569	0	0
T84	347713	44763	0	0
T85	169890	20350	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376859819	30398629	0	0
DepthKnown_A	376859819	376766100	0	0
RvalidKnown_A	376859819	376766100	0	0
WreadyKnown_A	376859819	376766100	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	30398629	0	0
T1	522530	32911	0	0
T2	542145	350463	0	0
T3	272356	25942	0	0
T55	151239	17068	0	0
T59	155970	17882	0	0
T81	219720	18508	0	0
T82	224587	20972	0	0
T83	127168	14194	0	0
T84	347713	42232	0	0
T85	169890	14448	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376859819	22343702	0	0
DepthKnown_A	376859819	376766100	0	0
RvalidKnown_A	376859819	376766100	0	0
WreadyKnown_A	376859819	376766100	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	22343702	0	0
T1	522530	19847	0	0
T2	542145	374880	0	0
T3	272356	18601	0	0
T55	151239	8538	0	0
T59	155970	9124	0	0
T81	219720	23440	0	0
T82	224587	16402	0	0
T83	127168	6448	0	0
T84	347713	34651	0	0
T85	169890	11541	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376859819	21850435	0	0
DepthKnown_A	376859819	376766100	0	0
RvalidKnown_A	376859819	376766100	0	0
WreadyKnown_A	376859819	376766100	0	0
gen_passthru_fifo.paramCheckPass	881	881	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	21850435	0	0
T1	522530	19089	0	0
T2	542145	374149	0	0
T3	272356	18211	0	0
T55	151239	8264	0	0
T59	155970	8850	0	0
T81	219720	23238	0	0
T82	224587	16031	0	0
T83	127168	6174	0	0
T84	347713	34507	0	0
T85	169890	11169	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376859819	376766100	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467625759	84044	0	0
DepthKnown_A	467625759	467519939	0	0
RvalidKnown_A	467625759	467519939	0	0
WreadyKnown_A	467625759	467519939	0	0
gen_passthru_fifo.paramCheckPass	2771	2771	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	84044	0	0
T1	522530	181	0	0
T2	542145	27	0	0
T3	272356	149	0	0
T55	151239	26	0	0
T59	155970	26	0	0
T81	219720	53	0	0
T82	224587	104	0	0
T83	127168	26	0	0
T84	347713	158	0	0
T85	169890	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2771	2771	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467625759	86813	0	0
DepthKnown_A	467625759	467519939	0	0
RvalidKnown_A	467625759	467519939	0	0
WreadyKnown_A	467625759	467519939	0	0
gen_passthru_fifo.paramCheckPass	2771	2771	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	86813	0	0
T1	522530	181	0	0
T2	542145	27	0	0
T3	272356	149	0	0
T55	151239	26	0	0
T59	155970	26	0	0
T81	219720	53	0	0
T82	224587	104	0	0
T83	127168	26	0	0
T84	347713	158	0	0
T85	169890	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2771	2771	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467625759	47410	0	0
DepthKnown_A	467625759	467519939	0	0
RvalidKnown_A	467625759	467519939	0	0
WreadyKnown_A	467625759	467519939	0	0
gen_passthru_fifo.paramCheckPass	2771	2771	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	47410	0	0
T1	522530	176	0	0
T2	542145	25	0	0
T3	272356	95	0	0
T55	151239	23	0	0
T59	155970	23	0	0
T81	219720	52	0	0
T82	224587	98	0	0
T83	127168	23	0	0
T84	347713	12	0	0
T85	169890	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2771	2771	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467625759	47410	0	0
DepthKnown_A	467625759	467519939	0	0
RvalidKnown_A	467625759	467519939	0	0
WreadyKnown_A	467625759	467519939	0	0
gen_passthru_fifo.paramCheckPass	2771	2771	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	47410	0	0
T1	522530	176	0	0
T2	542145	25	0	0
T3	272356	95	0	0
T55	151239	23	0	0
T59	155970	23	0	0
T81	219720	52	0	0
T82	224587	98	0	0
T83	127168	23	0	0
T84	347713	12	0	0
T85	169890	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2771	2771	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467625759	36634	0	0
DepthKnown_A	467625759	467519939	0	0
RvalidKnown_A	467625759	467519939	0	0
WreadyKnown_A	467625759	467519939	0	0
gen_passthru_fifo.paramCheckPass	2771	2771	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	36634	0	0
T1	522530	5	0	0
T2	542145	2	0	0
T3	272356	54	0	0
T55	151239	3	0	0
T59	155970	3	0	0
T81	219720	1	0	0
T82	224587	6	0	0
T83	127168	3	0	0
T84	347713	146	0	0
T85	169890	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2771	2771	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467625759	39403	0	0
DepthKnown_A	467625759	467519939	0	0
RvalidKnown_A	467625759	467519939	0	0
WreadyKnown_A	467625759	467519939	0	0
gen_passthru_fifo.paramCheckPass	2771	2771	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	39403	0	0
T1	522530	5	0	0
T2	542145	2	0	0
T3	272356	54	0	0
T55	151239	3	0	0
T59	155970	3	0	0
T81	219720	1	0	0
T82	224587	6	0	0
T83	127168	3	0	0
T84	347713	146	0	0
T85	169890	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467625759	467519939	0	0
T1	522530	522238	0	0
T2	542145	542128	0	0
T3	272356	272236	0	0
T55	151239	151181	0	0
T59	155970	155919	0	0
T81	219720	219662	0	0
T82	224587	224474	0	0
T83	127168	127106	0	0
T84	347713	347658	0	0
T85	169890	169777	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2771	2771	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T59	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0