Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T81,T169	Yes	T1,T81,T169	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T81,T169	Yes	T1,T81,T169	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T74,*T75	Yes	T2,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T48,T76	Yes	T75,T48,T76	INPUT
tl_i.a_valid	Yes	Yes	T1,T81,T169	Yes	T1,T81,T169	INPUT
tl_o.a_ready	Yes	Yes	T1,T81,T169	Yes	T1,T81,T169	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T81,T169	Yes	T1,T81,T169	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T81,T169	Yes	T1,T81,T169	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T81,T169	Yes	T1,T81,T169	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T81,*T169	Yes	T1,T81,T169	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T81,T169	Yes	T1,T81,T169	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T77,T344,T281	Yes	T77,T344,T281	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T78,T150	Yes	T77,T78,T150	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T78,T150	Yes	T77,T78,T150	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T77,T344,T281	Yes	T77,T344,T281	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T81,T169,T111	Yes	T81,T169,T111	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T1,T81,T169	Yes	T1,T81,T169	OUTPUT
intr_rx_watermark_o	Yes	Yes	T81,T169,T111	Yes	T81,T169,T111	OUTPUT
intr_tx_empty_o	Yes	Yes	T81,T169,T111	Yes	T81,T169,T111	OUTPUT
intr_rx_overflow_o	Yes	Yes	T81,T169,T111	Yes	T81,T169,T111	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T41,T111	Yes	T1,T41,T111	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T41,T111	Yes	T1,T41,T111	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T74,*T75	Yes	T2,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T48,T76	Yes	T75,T48,T76	INPUT
tl_i.a_valid	Yes	Yes	T1,T41,T111	Yes	T1,T41,T111	INPUT
tl_o.a_ready	Yes	Yes	T1,T41,T111	Yes	T1,T41,T111	OUTPUT
tl_o.d_error	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T111,T100	Yes	T1,T111,T100	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T111,T100	Yes	T1,T41,T111	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T111,T100	Yes	T1,T41,T111	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T73,T146	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T111,*T100	Yes	T1,T111,T100	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T41,T111	Yes	T1,T41,T111	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T77,T78,T330	Yes	T77,T78,T330	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T77,T78,T330	Yes	T77,T78,T330	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T111,T100,T189	Yes	T111,T100,T189	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T1,T111,T100	Yes	T1,T111,T100	OUTPUT
intr_rx_watermark_o	Yes	Yes	T111,T100,T189	Yes	T111,T100,T189	OUTPUT
intr_tx_empty_o	Yes	Yes	T111,T100,T189	Yes	T111,T100,T189	OUTPUT
intr_rx_overflow_o	Yes	Yes	T111,T100,T189	Yes	T111,T100,T189	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T169,T184,T302	Yes	T169,T184,T302	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T169,T184,T302	Yes	T169,T184,T302	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T74,*T75	Yes	T2,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T48,T76	Yes	T75,T48,T76	INPUT
tl_i.a_valid	Yes	Yes	T169,T184,T217	Yes	T169,T184,T217	INPUT
tl_o.a_ready	Yes	Yes	T169,T184,T217	Yes	T169,T184,T217	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T169,T184,T302	Yes	T169,T184,T302	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T169,T184,T217	Yes	T169,T184,T217	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T169,T184,T217	Yes	T169,T184,T217	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T73,T146	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T169,*T184,*T302	Yes	T169,T184,T302	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T169,T184,T217	Yes	T169,T184,T217	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T77,T281,T78	Yes	T77,T281,T78	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T78,T150	Yes	T77,T78,T150	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T78,T150	Yes	T77,T78,T150	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T77,T281,T78	Yes	T77,T281,T78	OUTPUT
cio_rx_i	Yes	Yes	T169,T32,T184	Yes	T169,T6,T32	INPUT
cio_tx_o	Yes	Yes	T169,T184,T302	Yes	T169,T184,T302	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T169,T184,T302	Yes	T169,T184,T302	OUTPUT
intr_rx_watermark_o	Yes	Yes	T169,T184,T302	Yes	T169,T184,T302	OUTPUT
intr_tx_empty_o	Yes	Yes	T169,T184,T302	Yes	T169,T184,T302	OUTPUT
intr_rx_overflow_o	Yes	Yes	T169,T184,T302	Yes	T169,T184,T302	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T74,*T75	Yes	T2,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T48,T76	Yes	T75,T48,T76	INPUT
tl_i.a_valid	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	INPUT
tl_o.a_ready	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T73,T146	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T81,*T179,*T276	Yes	T81,T179,T276	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T77,T344,T78	Yes	T77,T344,T78	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T78,T150	Yes	T77,T78,T150	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T78,T150	Yes	T77,T78,T150	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T77,T344,T78	Yes	T77,T344,T78	OUTPUT
cio_rx_i	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	INPUT
cio_tx_o	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
intr_rx_watermark_o	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
intr_tx_empty_o	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
intr_rx_overflow_o	Yes	Yes	T81,T179,T276	Yes	T81,T179,T276	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T74,*T75	Yes	T2,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T48,T76	Yes	T75,T48,T76	INPUT
tl_i.a_valid	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	INPUT
tl_o.a_ready	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T12,*T14,*T297	Yes	T12,T14,T297	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T77,T78,T362	Yes	T77,T78,T362	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T78,T152	Yes	T77,T78,T152	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T78,T152	Yes	T77,T78,T152	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T77,T78,T362	Yes	T77,T78,T362	OUTPUT
cio_rx_i	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	INPUT
cio_tx_o	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
intr_rx_watermark_o	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
intr_tx_empty_o	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
intr_rx_overflow_o	Yes	Yes	T12,T14,T297	Yes	T12,T14,T297	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T295,T306	Yes	T293,T295,T306	OUTPUT

*Tests covering at least one bit in the range