Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T146,T222,T223	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T224,T225,T226	Yes	T224,T225,T226	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T60,T5,T193	Yes	T60,T5,T193	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T60,T5,T193	Yes	T60,T5,T193	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T75,T48,T76	Yes	T75,T48,T76	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T76,T71,T225	Yes	T76,T71,T72	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T76,T71,T72	Yes	T76,T71,T72	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T3,T60,T61	Yes	T3,T60,T61	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T2,T66,T704	Yes	T2,T66,T704	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T2,T66,T704	Yes	T2,T66,T704	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T2,T66,T704	Yes	T2,T66,T704	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T2,T66,T704	Yes	T2,T66,T704	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T66,T704	Yes	T2,T66,T704	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T66,T704,T74	Yes	T66,T704,T74	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T2,*T66,*T704	Yes	T2,T66,T704	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T2,T66,T704	Yes	T2,T66,T704	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T50,T71,T72	Yes	T50,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T48,*T50,T71	Yes	T48,T50,T71	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T48,T50,T146	Yes	T48,T50,T71	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T48,*T50,T71	Yes	T48,T50,T71	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T48,*T50,*T71	Yes	T48,T50,T71	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T74,T48,T232	Yes	T74,T48,T232	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T48,T232	Yes	T74,T48,T232	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T74,T48,T232	Yes	T74,T48,T232	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T74,T48,T232	Yes	T74,T48,T232	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T74,T48,T232	Yes	T74,T48,T232	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T74,*T232,*T233	Yes	T74,T232,T233	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T74,T48,T232	Yes	T74,T48,T232	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T74,T232,T233	Yes	T74,T232,T233	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T48,T232	Yes	T74,T48,T232	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T74,*T232,*T233	Yes	T74,T232,T233	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T74,T48,T232	Yes	T74,T48,T232	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T163,T164,T75	Yes	T163,T164,T75	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T48,T56,T57	Yes	T48,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T391,T48,T364	Yes	T391,T48,T364	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T391,T48,T364	Yes	T391,T48,T364	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T48,T56,T57	Yes	T48,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T391,T48,T364	Yes	T391,T48,T364	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T48,*T50,T71	Yes	T48,T50,T71	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T391,T48,T364	Yes	T391,T48,T364	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T391,T48,T364	Yes	T391,T48,T364	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T391,T364,T251	Yes	T391,T364,T251	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T50,T71	Yes	T48,T56,T57	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T391,T48,T364	Yes	T391,T48,T364	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T48,*T50,T71	Yes	T48,T50,T71	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T48,*T251,*T93	Yes	T391,T48,T364	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T391,T48,T364	Yes	T391,T48,T364	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T2,*T74,*T75	Yes	T2,T74,T75	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T75,T48,T76	Yes	T75,T48,T76	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T3,T220,T320	Yes	T3,T220,T320	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T2,*T74,*T75	Yes	T2,T74,T75	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T1,T9,T147	Yes	T1,T9,T147	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T9,T147,T10	Yes	T9,T147,T10	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T9,T147	Yes	T1,T9,T147	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T9,T147	Yes	T1,T9,T147	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T9,T147,T10	Yes	T9,T147,T10	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T1,T9,T147	Yes	T1,T9,T147	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T9,T181,T192	Yes	T9,T181,T192	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T1,T9,T147	Yes	T1,T9,T147	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T1,T9,T147	Yes	T1,T9,T147	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T9,T147,T10	Yes	T9,T147,T10	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T9,T147	Yes	T1,T9,T147	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T9,T147,T10	Yes	T9,T147,T10	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T1,*T9,*T147	Yes	T1,T9,T147	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T1,T9,T147	Yes	T1,T9,T147	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T1,T32,T147	Yes	T1,T32,T147	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T32,T147,T148	Yes	T32,T147,T148	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T32,T147	Yes	T1,T32,T147	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T32,T147	Yes	T1,T32,T147	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T32,T147,T148	Yes	T32,T147,T148	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T1,T32,T147	Yes	T1,T32,T147	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T1,T32,T147	Yes	T1,T32,T147	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T1,T32,T147	Yes	T1,T32,T147	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T71,T73,T146	Yes	T71,T72,T73	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T32,T147,T148	Yes	T32,T147,T148	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T32,T147	Yes	T1,T32,T147	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T32,T147,T148	Yes	T32,T147,T148	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T1,*T32,*T147	Yes	T1,T32,T147	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T1,T32,T147	Yes	T1,T32,T147	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T1,T15,T216	Yes	T1,T15,T216	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T1,T15,T216	Yes	T1,T15,T216	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T15,T216	Yes	T1,T15,T216	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T1,T15,T216	Yes	T1,T15,T216	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T1,T15,T216	Yes	T1,T15,T216	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T1,T15,T216	Yes	T1,T15,T216	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T1,T15,T216	Yes	T1,T15,T216	INPUT
tl_usbdev_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T1,T216,T371	Yes	T1,T216,T371	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T216,T371	Yes	T1,T216,T371	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T1,T15,T216	Yes	T1,T15,T216	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T1,*T15,*T216	Yes	T1,T15,T216	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T1,T15,T216	Yes	T1,T15,T216	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T73,T146	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T73,T146	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T73,T146	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T73,T146	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T146,T222,T223	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T71,T73,T146	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T71,T73,T146	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T41,T102,T703	Yes	T41,T102,T703	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T41,T102,T703	Yes	T41,T102,T703	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T41,T102,T280	Yes	T41,T102,T280	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T41,T102,T703	Yes	T41,T102,T703	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T41,T102,T280	Yes	T41,T102,T280	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T102,T703,T327	Yes	T102,T703,T327	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T41,T102,T280	Yes	T41,T102,T280	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T41,T102,T280	Yes	T41,T102,T280	INPUT
tl_hmac_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T41,T102,T280	Yes	T41,T102,T280	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T102,T280	Yes	T41,T102,T280	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T41,T102,T703	Yes	T41,T102,T703	INPUT
tl_hmac_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T73,T146	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T41,*T102,*T703	Yes	T41,T102,T703	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T41,T102,T280	Yes	T41,T102,T280	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T147,T194,T275	Yes	T147,T194,T275	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T118,T99,T280	Yes	T118,T99,T280	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T118,T99,T280	Yes	T118,T99,T280	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T147,T275,T277	Yes	T147,T275,T277	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T118,T99,T280	Yes	T118,T99,T280	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T275,T277,T196	Yes	T275,T277,T196	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T118,T99,T280	Yes	T118,T99,T280	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T118,T99,T280	Yes	T118,T99,T280	INPUT
tl_kmac_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T118,T99,T147	Yes	T118,T99,T147	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T118,T99,T147	Yes	T118,T99,T147	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T118,T99,T147	Yes	T147,T275,T277	INPUT
tl_kmac_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T71,T73,T146	Yes	T71,T72,T73	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T118,*T99,*T147	Yes	T147,T275,T277	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T118,T99,T147	Yes	T118,T99,T147	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T502,*T71,*T72	Yes	T502,T71,T72	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	INPUT
tl_aes_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T266,T384,T280	Yes	T266,T118,T99	INPUT
tl_aes_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T502,*T71,*T72	Yes	T502,T71,T72	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T266,*T118,*T99	Yes	T266,T118,T99	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T266,T118,T99	Yes	T266,T118,T99	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T71,T72,T146	Yes	T71,T72,T146	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T84,*T118,*T99	Yes	T84,T41,T118	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T502,*T71,*T73	Yes	T502,T71,T73	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T71,T73,T146	Yes	T71,T72,T73	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T502,*T71,*T73	Yes	T502,T71,T72	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T84,*T118,*T99	Yes	T84,T118,T99	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T84,*T118,*T99	Yes	T84,T118,T99	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	INPUT
tl_edn1_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	INPUT
tl_edn1_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T84,*T118,*T99	Yes	T84,T118,T99	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T84,T118,T99	Yes	T84,T118,T99	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T81,T12	Yes	T3,T81,T12	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T71,T73,T146	Yes	T71,T72,T73	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T55,*T59	Yes	T3,T55,T59	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T393	Yes	T75,T76,T393	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	INPUT
tl_otbn_i.d_error	Yes	Yes	T71,T73,T146	Yes	T71,T72,T73	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	INPUT
tl_otbn_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T393	Yes	T75,T76,T393	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T41,*T118,*T99	Yes	T41,T118,T99	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T118,T99,T147	Yes	T118,T99,T147	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	INPUT
tl_keymgr_i.d_error	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T118,T99,T147	Yes	T118,T99,T147	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T71,*T73,*T146	Yes	T71,T72,T73	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T41,*T118,*T99	Yes	T41,T118,T99	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T41,T118,T99	Yes	T41,T118,T99	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T48,*T50,*T71	Yes	T48,T50,T71	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T48,T50,T71	Yes	T48,T50,T71	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T3,T55,T59	Yes	T3,T55,T59	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T48,*T50,*T71	Yes	T48,T50,T71	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T82,T85,T41	Yes	T82,T85,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T82,T85,T41	Yes	T82,T85,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T82,T85,T41	Yes	T82,T85,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T82,T85,T41	Yes	T82,T85,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T82,T85,T41	Yes	T82,T85,T41	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T71,T73,T146	Yes	T71,T73,T146	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T82,T85,T41	Yes	T82,T85,T41	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T82,T85,T41	Yes	T82,T85,T41	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T5,T172,T279	Yes	T5,T172,T279	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T82,T85,T5	Yes	T82,T85,T41	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T82,T85,T5	Yes	T82,T85,T41	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T82,*T85,*T5	Yes	T82,T85,T392	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T82,T85,T41	Yes	T82,T85,T41	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range