Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.79 96.47 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 84.62 100.00 100.00 u_edn_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00

Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 753719638 3038 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 753719638 3038 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 753719638 3038 0 0
T1 522530 5 0 0
T2 542145 2 0 0
T3 272356 4 0 0
T18 181678 0 0 0
T55 151239 2 0 0
T59 155970 2 0 0
T81 219720 1 0 0
T82 224587 4 0 0
T83 127168 2 0 0
T84 347713 81 0 0
T85 169890 4 0 0
T171 94635 3 0 0
T172 278932 0 0 0
T173 0 11 0 0
T174 0 4 0 0
T190 119248 0 0 0
T270 0 4 0 0
T271 0 9 0 0
T272 0 4 0 0
T273 158603 0 0 0
T274 552253 0 0 0
T275 82159 0 0 0
T276 110623 0 0 0
T277 88033 0 0 0
T278 154449 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 753719638 3038 0 0
T1 522530 5 0 0
T2 542145 2 0 0
T3 272356 4 0 0
T18 181678 0 0 0
T55 151239 2 0 0
T59 155970 2 0 0
T81 219720 1 0 0
T82 224587 4 0 0
T83 127168 2 0 0
T84 347713 81 0 0
T85 169890 4 0 0
T171 94635 3 0 0
T172 278932 0 0 0
T173 0 11 0 0
T174 0 4 0 0
T190 119248 0 0 0
T270 0 4 0 0
T271 0 9 0 0
T272 0 4 0 0
T273 158603 0 0 0
T274 552253 0 0 0
T275 82159 0 0 0
T276 110623 0 0 0
T277 88033 0 0 0
T278 154449 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 376859819 35 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 376859819 35 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 376859819 35 0 0
T18 181678 0 0 0
T171 94635 3 0 0
T172 278932 0 0 0
T173 0 11 0 0
T174 0 4 0 0
T190 119248 0 0 0
T270 0 4 0 0
T271 0 9 0 0
T272 0 4 0 0
T273 158603 0 0 0
T274 552253 0 0 0
T275 82159 0 0 0
T276 110623 0 0 0
T277 88033 0 0 0
T278 154449 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 376859819 35 0 0
T18 181678 0 0 0
T171 94635 3 0 0
T172 278932 0 0 0
T173 0 11 0 0
T174 0 4 0 0
T190 119248 0 0 0
T270 0 4 0 0
T271 0 9 0 0
T272 0 4 0 0
T273 158603 0 0 0
T274 552253 0 0 0
T275 82159 0 0 0
T276 110623 0 0 0
T277 88033 0 0 0
T278 154449 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 376859819 3003 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 376859819 3003 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 376859819 3003 0 0
T1 522530 5 0 0
T2 542145 2 0 0
T3 272356 4 0 0
T55 151239 2 0 0
T59 155970 2 0 0
T81 219720 1 0 0
T82 224587 4 0 0
T83 127168 2 0 0
T84 347713 81 0 0
T85 169890 4 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 376859819 3003 0 0
T1 522530 5 0 0
T2 542145 2 0 0
T3 272356 4 0 0
T55 151239 2 0 0
T59 155970 2 0 0
T81 219720 1 0 0
T82 224587 4 0 0
T83 127168 2 0 0
T84 347713 81 0 0
T85 169890 4 0 0

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