Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3307877	1			T75	183		T76	1100		T77	1496
values[2]	676772	1			T75	18		T77	610		T139	434
values[3]	98585	1			T75	4		T77	249		T139	3
values[4]	50251	1			T77	86		T210	1		T416	275
values[5]	33958	1			T77	45		T416	103		T395	140
values[6]	25728	1			T77	48		T416	64		T395	138
values[7]	20754	1			T77	38		T416	31		T395	122
values[8]	17557	1			T77	24		T416	11		T395	101
values[9]	15709	1			T77	17		T416	6		T395	91
values[10]	13865	1			T77	15		T416	3		T395	85
values[11]	13265	1			T77	19		T416	2		T395	63
values[12]	12875	1			T77	20		T416	4		T395	41
values[13]	11919	1			T77	14		T416	1		T395	53
values[14]	11256	1			T77	16		T395	62		T381	26
values[15]	10920	1			T77	2		T395	46		T381	38
values[16]	11030	1			T395	46		T381	40		T605	14
values[17]	10584	1			T395	32		T381	34		T605	16
values[18]	10068	1			T395	28		T381	58		T605	16
values[19]	9520	1			T395	43		T381	40		T605	24
values[20]	9410	1			T395	49		T381	35		T605	31
values[21]	9105	1			T395	30		T381	25		T605	22
values[22]	8757	1			T395	15		T381	38		T605	15
values[23]	8307	1			T395	10		T381	46		T605	8
values[24]	8130	1			T395	29		T381	37		T605	10
values[25]	7830	1			T395	24		T381	34		T605	15
values[26]	7573	1			T395	27		T381	20		T605	14
values[27]	6964	1			T395	26		T381	26		T605	14
values[28]	6429	1			T395	41		T381	11		T605	7
values[29]	6240	1			T395	31		T381	13		T605	6
values[30]	5721	1			T395	39		T381	32		T605	9
values[31]	5235	1			T395	35		T381	22		T605	13
values[32]	4989	1			T395	36		T381	34		T605	16
values[33]	4734	1			T395	21		T381	18		T605	22
values[34]	4321	1			T395	17		T381	10		T605	18
values[35]	4032	1			T395	23		T381	11		T605	12
values[36]	3849	1			T395	11		T381	7		T605	11
values[37]	3608	1			T395	13		T381	4		T605	11
values[38]	3528	1			T395	20		T381	5		T605	13
values[39]	3358	1			T395	23		T381	11		T605	9
values[40]	3258	1			T395	21		T381	9		T605	9
values[41]	3144	1			T395	20		T381	4		T605	10
values[42]	3083	1			T395	15		T381	9		T605	10
values[43]	3042	1			T395	7		T381	7		T605	12
values[44]	2949	1			T395	7		T381	4		T605	20
values[45]	2853	1			T395	8		T381	7		T605	5
values[46]	2795	1			T395	7		T381	6		T605	14
values[47]	2696	1			T395	14		T381	9		T605	12
values[48]	2572	1			T395	6		T381	6		T605	10
values[49]	2576	1			T395	11		T381	10		T605	12
values[50]	2636	1			T395	12		T381	13		T605	16
values[51]	2429	1			T395	15		T381	10		T605	10
values[52]	2473	1			T395	15		T381	8		T605	10
values[53]	2476	1			T395	15		T381	12		T605	14
values[54]	2423	1			T395	7		T381	5		T605	12
values[55]	2381	1			T395	7		T381	2		T605	10
values[56]	2335	1			T395	11		T381	2		T605	14
values[57]	2272	1			T395	10		T605	11		T382	11
values[58]	2170	1			T395	6		T605	17		T382	8
values[59]	2209	1			T395	7		T605	13		T382	6
values[60]	2229	1			T395	7		T605	7		T382	5
values[61]	2476	1			T395	7		T605	4		T382	8
values[62]	3878	1			T395	43		T605	15		T382	23
values[63]	14366	1			T395	85		T605	87		T382	104
values[64]	206689	1			T395	172		T605	245		T382	214

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4288043	1			T75	572		T76	1125		T77	3174
values[2]	718024	1			T75	99		T77	595		T139	477
values[3]	69189	1			T75	6		T77	78		T139	19
values[4]	12728	1			T75	4		T77	2		T139	1
values[5]	4757	1			T75	3		T210	2		T416	4
values[6]	2845	1			T75	11		T416	1		T395	63
values[7]	2026	1			T75	16		T395	49		T501	2
values[8]	1716	1			T75	16		T395	57		T501	2
values[9]	1419	1			T75	18		T395	40		T501	3
values[10]	1232	1			T75	11		T395	24		T501	2
values[11]	1069	1			T75	12		T395	21		T501	2
values[12]	1014	1			T75	3		T395	29		T501	2
values[13]	1058	1			T75	3		T395	23		T501	2
values[14]	996	1			T395	25		T501	2		T422	2
values[15]	941	1			T395	16		T501	2		T422	2
values[16]	951	1			T395	15		T501	2		T422	2
values[17]	834	1			T395	7		T501	1		T422	2
values[18]	782	1			T395	5		T501	1		T422	2
values[19]	784	1			T395	1		T501	2		T422	2
values[20]	736	1			T395	1		T501	2		T422	2
values[21]	771	1			T395	1		T501	2		T422	2
values[22]	685	1			T395	2		T501	2		T422	2
values[23]	626	1			T395	1		T501	2		T422	2
values[24]	656	1			T501	2		T422	2		T394	18
values[25]	721	1			T501	2		T422	2		T394	16
values[26]	695	1			T501	2		T422	2		T394	11
values[27]	650	1			T501	2		T422	2		T394	11
values[28]	615	1			T501	2		T422	2		T394	9
values[29]	562	1			T501	2		T422	2		T394	21
values[30]	540	1			T501	2		T422	2		T394	10
values[31]	451	1			T501	2		T422	2		T394	13
values[32]	472	1			T501	3		T422	2		T394	16
values[33]	454	1			T501	2		T422	2		T394	12
values[34]	445	1			T501	2		T422	2		T394	22
values[35]	430	1			T501	2		T422	2		T394	20
values[36]	441	1			T501	2		T422	2		T394	13
values[37]	422	1			T501	2		T422	2		T394	8
values[38]	386	1			T501	2		T422	2		T394	6
values[39]	420	1			T501	2		T422	2		T394	3
values[40]	404	1			T501	3		T422	2		T394	5
values[41]	436	1			T501	2		T422	2		T394	6
values[42]	408	1			T501	2		T422	2		T394	12
values[43]	377	1			T501	2		T422	2		T394	11
values[44]	410	1			T501	2		T422	2		T394	9
values[45]	374	1			T501	2		T422	2		T394	8
values[46]	367	1			T501	1		T422	2		T394	10
values[47]	370	1			T422	2		T394	8		T651	2
values[48]	367	1			T422	2		T394	2		T651	2
values[49]	373	1			T422	2		T394	6		T651	2
values[50]	344	1			T422	2		T394	3		T651	2
values[51]	375	1			T422	2		T394	2		T651	2
values[52]	364	1			T422	2		T394	1		T651	1
values[53]	328	1			T422	2		T394	3		T651	1
values[54]	332	1			T422	2		T394	1		T651	2
values[55]	309	1			T422	2		T394	1		T651	2
values[56]	317	1			T422	2		T394	3		T651	2
values[57]	347	1			T422	2		T394	2		T651	2
values[58]	324	1			T422	2		T394	2		T651	2
values[59]	332	1			T422	2		T394	5		T651	1
values[60]	352	1			T422	2		T394	1		T651	1
values[61]	344	1			T422	2		T394	2		T651	2
values[62]	556	1			T422	2		T394	3		T651	3
values[63]	2648	1			T422	2		T394	8		T651	8
values[64]	26561	1			T422	328		T394	7		T651	160

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	534175	1			T75	6		T76	1055		T77	214
values[2]	2331938	1			T75	166		T77	1388		T139	1586
values[3]	1061584	1			T75	20		T77	663		T139	408
values[4]	134898	1			T75	7		T77	213		T139	2
values[5]	67779	1			T75	3		T77	72		T210	1
values[6]	43924	1			T75	9		T77	54		T416	153
values[7]	32291	1			T75	11		T77	26		T416	99
values[8]	25591	1			T75	5		T77	22		T416	62
values[9]	21617	1			T75	17		T77	33		T416	19
values[10]	18578	1			T75	23		T77	20		T416	10
values[11]	17101	1			T75	22		T77	21		T416	6
values[12]	16096	1			T75	17		T77	7		T416	2
values[13]	15033	1			T75	7		T77	3		T395	59
values[14]	14082	1			T75	11		T77	1		T395	44
values[15]	13004	1			T75	9		T395	30		T381	50
values[16]	12298	1			T75	8		T395	47		T381	41
values[17]	11630	1			T75	7		T395	46		T381	34
values[18]	11248	1			T75	1		T395	43		T381	42
values[19]	10829	1			T395	40		T381	32		T605	14
values[20]	10350	1			T395	32		T381	31		T605	16
values[21]	10072	1			T395	16		T381	28		T605	18
values[22]	9709	1			T395	31		T381	35		T605	21
values[23]	9299	1			T395	40		T381	32		T605	35
values[24]	9289	1			T395	32		T381	36		T605	17
values[25]	9031	1			T395	35		T381	72		T605	19
values[26]	8637	1			T395	29		T381	69		T605	20
values[27]	8219	1			T395	15		T381	46		T605	25
values[28]	7659	1			T395	9		T381	31		T605	30
values[29]	7209	1			T395	14		T381	19		T605	26
values[30]	6701	1			T395	12		T381	12		T605	18
values[31]	6190	1			T395	12		T381	22		T605	14
values[32]	5607	1			T395	15		T381	9		T605	12
values[33]	5204	1			T395	14		T381	2		T605	10
values[34]	4890	1			T395	17		T381	5		T605	8
values[35]	4494	1			T395	22		T381	1		T605	14
values[36]	4065	1			T395	21		T381	2		T605	17
values[37]	3905	1			T395	19		T381	1		T605	29
values[38]	3585	1			T395	15		T381	4		T605	23
values[39]	3494	1			T395	12		T381	1		T605	8
values[40]	3422	1			T395	10		T381	4		T605	10
values[41]	3412	1			T395	14		T381	6		T605	21
values[42]	3208	1			T395	11		T381	2		T605	13
values[43]	3248	1			T395	11		T605	7		T382	7
values[44]	3098	1			T395	19		T605	18		T382	8
values[45]	3195	1			T395	21		T605	25		T382	14
values[46]	3083	1			T395	34		T605	21		T382	14
values[47]	3047	1			T395	25		T605	25		T382	13
values[48]	3035	1			T395	12		T605	17		T382	17
values[49]	2909	1			T395	16		T605	20		T382	10
values[50]	2861	1			T395	17		T605	20		T382	10
values[51]	2817	1			T395	12		T605	18		T382	5
values[52]	2649	1			T395	26		T605	20		T382	6
values[53]	2639	1			T395	27		T605	7		T382	8
values[54]	2600	1			T395	16		T605	10		T382	13
values[55]	2551	1			T395	9		T605	9		T382	8
values[56]	2539	1			T395	10		T605	11		T382	10
values[57]	2406	1			T395	8		T605	11		T382	6
values[58]	2507	1			T395	7		T605	8		T382	9
values[59]	2455	1			T395	9		T605	7		T382	8
values[60]	2467	1			T395	7		T605	10		T382	9
values[61]	2519	1			T395	14		T605	5		T382	7
values[62]	3613	1			T395	32		T605	17		T382	35
values[63]	17780	1			T395	84		T605	91		T382	115
values[64]	198229	1			T395	253		T605	173		T382	251