Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1719708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21614118

1

T1

7231

T2

9756

T3

32834

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14824203	1			T1	3210		T2	3253		T3	23030
values[0x0]	7067681	1			T1	4021		T2	6503		T3	9804
values[0x1]	1441942	1			T1	328		T2	457		T3	73

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	483184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22850642

1

T1

7559

T2

10213

T3

32907

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10667851	1			T1	3780		T2	5107		T3	16454
valid_sources[0x01]	10667743	1			T1	3779		T2	5106		T3	16453
valid_sources[0x02]	32101	1			T497	13		T516	8		T122	97
valid_sources[0x03]	31633	1			T52	1		T53	2		T497	15
valid_sources[0x04]	31977	1			T52	2		T497	12		T516	10
valid_sources[0x05]	32464	1			T497	20		T516	7		T122	144
valid_sources[0x06]	31971	1			T53	1		T497	21		T516	8
valid_sources[0x07]	32264	1			T497	9		T516	11		T122	190
valid_sources[0x08]	32392	1			T78	1		T24	7		T497	14
valid_sources[0x09]	31281	1			T497	18		T516	10		T122	178
valid_sources[0x0a]	31812	1			T497	17		T516	9		T122	112
valid_sources[0x0b]	32845	1			T52	1		T497	12		T516	9
valid_sources[0x0c]	33028	1			T24	5		T497	17		T516	9
valid_sources[0x0d]	32341	1			T53	1		T497	17		T516	6
valid_sources[0x0e]	31712	1			T78	4		T24	7		T497	15
valid_sources[0x0f]	31590	1			T78	3		T24	1		T497	14
valid_sources[0x10]	32226	1			T52	1		T497	14		T516	13
valid_sources[0x11]	31350	1			T78	1		T52	1		T53	1
valid_sources[0x12]	32020	1			T52	2		T497	13		T516	10
valid_sources[0x13]	31774	1			T497	15		T516	8		T122	114
valid_sources[0x14]	32620	1			T78	2		T52	1		T53	1
valid_sources[0x15]	31355	1			T53	1		T497	15		T516	8
valid_sources[0x16]	30846	1			T78	2		T211	7		T497	15
valid_sources[0x17]	32732	1			T52	4		T24	2		T53	2
valid_sources[0x18]	32238	1			T53	1		T497	23		T516	6
valid_sources[0x19]	32099	1			T211	2		T497	17		T516	10
valid_sources[0x1a]	32021	1			T497	15		T516	7		T122	166
valid_sources[0x1b]	33686	1			T53	2		T497	18		T516	11
valid_sources[0x1c]	32754	1			T24	4		T53	2		T497	14
valid_sources[0x1d]	32492	1			T78	4		T52	1		T53	1
valid_sources[0x1e]	35614	1			T497	12		T516	14		T122	216
valid_sources[0x1f]	32450	1			T497	20		T516	15		T122	164
valid_sources[0x20]	31737	1			T52	1		T24	2		T497	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14321189

1

T1

3210

T2

3253

T3

23030

values[0x0]

all_enables

biggest_size

7025490

1

T1

4021

T2

6503

T3

9804

values[0x1]

all_enables

biggest_size

267439

1

T78

22

T52

22

T24

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2661478	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

420391

1

T75

1

T76

151

T77

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1043085	1			T75	5		T76	402		T77	52
values[0x0]	996622	1			T76	338		T77	9		T139	684
values[0x1]	1042162	1			T75	2		T76	360		T77	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2061230	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1020639

1

T75

1

T76

365

T77

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48579	1			T76	6		T77	1		T139	41
valid_sources[0x01]	47566	1			T76	23		T77	1		T139	28
valid_sources[0x02]	48493	1			T76	17		T77	3		T139	31
valid_sources[0x03]	48849	1			T77	3		T139	26		T413	15
valid_sources[0x04]	49090	1			T76	42		T139	47		T210	2
valid_sources[0x05]	48706	1			T76	19		T77	4		T139	21
valid_sources[0x06]	47683	1			T76	30		T139	28		T413	58
valid_sources[0x07]	47980	1			T76	37		T77	1		T139	29
valid_sources[0x08]	47056	1			T75	1		T77	4		T139	26
valid_sources[0x09]	48133	1			T77	1		T139	36		T410	19
valid_sources[0x0a]	47299	1			T77	1		T139	38		T413	4
valid_sources[0x0b]	47836	1			T76	8		T77	5		T139	32
valid_sources[0x0c]	47838	1			T76	17		T77	3		T139	30
valid_sources[0x0d]	47917	1			T76	39		T77	3		T139	23
valid_sources[0x0e]	47904	1			T75	2		T76	74		T77	2
valid_sources[0x0f]	47726	1			T77	3		T139	37		T210	2
valid_sources[0x10]	48381	1			T139	35		T410	28		T413	8
valid_sources[0x11]	47379	1			T76	20		T77	2		T139	37
valid_sources[0x12]	48248	1			T76	6		T77	2		T139	34
valid_sources[0x13]	48000	1			T76	19		T77	1		T139	29
valid_sources[0x14]	48551	1			T77	1		T139	32		T413	11
valid_sources[0x15]	48261	1			T76	25		T77	1		T139	33
valid_sources[0x16]	47925	1			T75	1		T77	1		T139	33
valid_sources[0x17]	48773	1			T76	32		T77	4		T139	34
valid_sources[0x18]	48538	1			T76	40		T139	35		T410	8
valid_sources[0x19]	48130	1			T76	38		T77	2		T139	34
valid_sources[0x1a]	48058	1			T76	17		T139	32		T410	18
valid_sources[0x1b]	48781	1			T76	11		T77	1		T139	31
valid_sources[0x1c]	48050	1			T76	12		T77	4		T139	38
valid_sources[0x1d]	48339	1			T76	25		T139	34		T413	10
valid_sources[0x1e]	47805	1			T76	47		T77	2		T139	29
valid_sources[0x1f]	46825	1			T139	25		T210	10		T413	37
valid_sources[0x20]	47768	1			T76	19		T139	29		T410	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43799

1

T76

14

T77

3

T139

21

values[0x0]

all_enables

biggest_size

332566

1

T76

114

T77

5

T139

224

values[0x1]

all_enables

biggest_size

44026

1

T75

1

T76

23

T77

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2839488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

461665

1

T75

4

T76

183

T77

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1130570	1			T75	24		T76	365		T77	76
values[0x0]	1043107	1			T75	2		T76	365		T77	14
values[0x1]	1127476	1			T75	16		T76	395		T77	78

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2179016	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1122137

1

T75

15

T76

408

T77

61

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52029	1			T75	1		T76	19		T77	2
valid_sources[0x01]	50723	1			T76	37		T77	2		T139	38
valid_sources[0x02]	51035	1			T76	7		T77	3		T139	30
valid_sources[0x03]	51185	1			T75	1		T77	2		T139	31
valid_sources[0x04]	51666	1			T76	34		T77	1		T139	32
valid_sources[0x05]	52252	1			T75	1		T76	28		T77	1
valid_sources[0x06]	52399	1			T76	36		T77	2		T139	39
valid_sources[0x07]	50397	1			T75	2		T76	40		T77	3
valid_sources[0x08]	51232	1			T75	3		T77	2		T139	35
valid_sources[0x09]	52120	1			T77	1		T139	36		T210	1
valid_sources[0x0a]	51248	1			T77	2		T139	28		T210	5
valid_sources[0x0b]	50827	1			T75	2		T76	14		T77	3
valid_sources[0x0c]	51652	1			T75	1		T76	31		T77	3
valid_sources[0x0d]	50737	1			T76	31		T77	5		T139	36
valid_sources[0x0e]	51946	1			T75	1		T76	72		T77	4
valid_sources[0x0f]	51818	1			T77	2		T139	23		T413	21
valid_sources[0x10]	51550	1			T75	1		T77	8		T139	38
valid_sources[0x11]	51387	1			T76	13		T77	2		T139	31
valid_sources[0x12]	52111	1			T75	2		T76	5		T77	1
valid_sources[0x13]	52144	1			T75	4		T76	17		T77	3
valid_sources[0x14]	51535	1			T77	9		T139	32		T210	3
valid_sources[0x15]	52348	1			T75	1		T76	28		T77	1
valid_sources[0x16]	51604	1			T75	4		T77	1		T139	39
valid_sources[0x17]	52369	1			T76	38		T77	4		T139	29
valid_sources[0x18]	51055	1			T76	50		T77	4		T139	40
valid_sources[0x19]	51129	1			T76	26		T77	2		T139	33
valid_sources[0x1a]	50922	1			T75	1		T76	6		T77	3
valid_sources[0x1b]	52185	1			T75	1		T76	20		T77	4
valid_sources[0x1c]	51552	1			T75	1		T76	18		T77	2
valid_sources[0x1d]	52481	1			T76	27		T77	2		T139	39
valid_sources[0x1e]	51249	1			T75	1		T76	48		T77	4
valid_sources[0x1f]	50874	1			T77	1		T139	40		T210	1
valid_sources[0x20]	51779	1			T76	7		T77	1		T139	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48477

1

T75

3

T76

11

T77

5

values[0x0]

all_enables

biggest_size

365113

1

T76

147

T77

9

T139

265

values[0x1]

all_enables

biggest_size

48075

1

T75

1

T76

25

T77

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2683209	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

424870

1

T75

2

T76

159

T77

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1050965	1			T75	9		T76	326		T77	51
values[0x0]	1006438	1			T75	1		T76	368		T77	11
values[0x1]	1050676	1			T75	4		T76	361		T77	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2077994	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1030085

1

T75

5

T76

363

T77

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48874	1			T75	1		T76	12		T77	3
valid_sources[0x01]	47377	1			T76	24		T77	1		T139	48
valid_sources[0x02]	48028	1			T76	17		T77	1		T139	33
valid_sources[0x03]	49009	1			T77	2		T139	65		T413	9
valid_sources[0x04]	49140	1			T76	36		T77	2		T139	22
valid_sources[0x05]	48446	1			T76	28		T77	1		T139	12
valid_sources[0x06]	49038	1			T76	27		T77	3		T139	28
valid_sources[0x07]	47594	1			T76	34		T77	3		T139	23
valid_sources[0x08]	48376	1			T77	4		T139	32		T410	28
valid_sources[0x09]	48816	1			T77	1		T139	18		T210	1
valid_sources[0x0a]	48917	1			T77	1		T139	22		T210	2
valid_sources[0x0b]	48685	1			T76	18		T77	1		T139	41
valid_sources[0x0c]	48373	1			T76	15		T139	24		T410	27
valid_sources[0x0d]	47896	1			T76	28		T139	6		T413	28
valid_sources[0x0e]	48871	1			T75	3		T76	61		T77	4
valid_sources[0x0f]	48563	1			T77	1		T139	22		T210	2
valid_sources[0x10]	48128	1			T75	1		T139	39		T410	25
valid_sources[0x11]	48067	1			T76	6		T77	1		T139	12
valid_sources[0x12]	48921	1			T76	10		T139	24		T210	3
valid_sources[0x13]	48563	1			T75	1		T76	20		T77	1
valid_sources[0x14]	48555	1			T77	2		T139	14		T210	7
valid_sources[0x15]	48615	1			T76	37		T139	50		T210	2
valid_sources[0x16]	48819	1			T75	2		T77	1		T139	26
valid_sources[0x17]	49117	1			T76	37		T77	3		T139	69
valid_sources[0x18]	48766	1			T76	29		T77	1		T139	26
valid_sources[0x19]	48363	1			T76	26		T77	1		T139	53
valid_sources[0x1a]	48286	1			T76	14		T139	63		T410	11
valid_sources[0x1b]	49703	1			T76	6		T77	3		T139	43
valid_sources[0x1c]	48794	1			T75	1		T76	12		T77	4
valid_sources[0x1d]	48763	1			T76	34		T77	5		T139	26
valid_sources[0x1e]	47915	1			T76	32		T77	4		T139	14
valid_sources[0x1f]	47746	1			T139	26		T210	1		T413	13
valid_sources[0x20]	48157	1			T76	7		T77	1		T139	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44611

1

T75

1

T76

11

T77

2

values[0x0]

all_enables

biggest_size

336202

1

T75

1

T76

128

T77

6

values[0x1]

all_enables

biggest_size

44057

1

T76

20

T77

4

T139

25