Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_device
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.21 88.21

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_spi_device 98.42 98.42


Module Instance : tb.dut.top_earlgrey.u_spi_device

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.42 98.42


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.42 98.42


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : spi_device
TotalCoveredPercent
Totals 61 50 81.97
Total Bits 424 374 88.21
Total Bits 0->1 212 187 88.21
Total Bits 1->0 212 187 88.21

Ports 61 50 81.97
Port Bits 424 374 88.21
Port Bits 0->1 212 187 88.21
Port Bits 1->0 212 187 88.21

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T62,T33 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[12:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T49,*T5,*T6 Yes T49,T5,T6 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T78,T52,T24 Yes T78,T52,T24 INPUT
tl_i.a_valid Yes Yes T5,T6,T14 Yes T5,T6,T14 INPUT
tl_o.a_ready Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
tl_o.d_error Yes Yes T76,T77,T139 Yes T76,T77,T139 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T77 Yes T76,T77,T139 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T6,*T14 Yes T5,T6,T14 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T79,T178,T179 Yes T79,T178,T179 INPUT
alert_rx_i[0].ping_n Yes Yes T79,T178,T82 Yes T79,T82,T180 INPUT
alert_rx_i[0].ping_p Yes Yes T79,T82,T180 Yes T79,T178,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T79,T178,T179 Yes T79,T178,T179 OUTPUT
cio_sck_i Yes Yes T5,T6,T14 Yes T5,T6,T7 INPUT
cio_csb_i Yes Yes T46,T5,T6 Yes T5,T6,T7 INPUT
cio_sd_o[3:0] Yes Yes T12,T181,T182 Yes T12,T181,T182 OUTPUT
cio_sd_en_o[3:0] Yes Yes T12,T181,T183 Yes T12,T181,T183 OUTPUT
cio_sd_i[3:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 INPUT
cio_tpm_csb_i Yes Yes T40,T41,T42 Yes T40,T41,T42 INPUT
passthrough_o.s_en[0] Yes Yes *T12,*T181,*T182 Yes T12,T181,T182 OUTPUT
passthrough_o.s_en[3:1] No No No OUTPUT
passthrough_o.s[3:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
passthrough_o.csb_en No No No OUTPUT
passthrough_o.csb Yes Yes T46,T5,T6 Yes T5,T6,T7 OUTPUT
passthrough_o.sck_en No No No OUTPUT
passthrough_o.sck Yes Yes T5,T6,T14 Yes T5,T6,T7 OUTPUT
passthrough_o.passthrough_en Yes Yes T183,T184,T185 Yes T12,T181,T182 OUTPUT
passthrough_i.s[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
intr_upload_cmdfifo_not_empty_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_upload_payload_not_empty_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_upload_payload_overflow_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_readbuf_watermark_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_readbuf_flip_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_tpm_header_not_empty_o Yes Yes T40,T142,T41 Yes T40,T142,T41 OUTPUT
intr_tpm_rdfifo_cmd_end_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_tpm_rdfifo_drop_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
ram_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
sck_monitor_o Yes Yes T5,T6,T14 Yes T5,T6,T7 OUTPUT
mbist_en_i Unreachable Unreachable Unreachable INPUT
scan_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_device
TotalCoveredPercent
Totals 51 50 98.04
Total Bits 380 374 98.42
Total Bits 0->1 190 187 98.42
Total Bits 1->0 190 187 98.42

Ports 51 50 98.04
Port Bits 380 374 98.42
Port Bits 0->1 190 187 98.42
Port Bits 1->0 190 187 98.42

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T62,T33 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[12:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T49,*T5,*T6 Yes T49,T5,T6 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T78,T52,T24 Yes T78,T52,T24 INPUT
tl_i.a_valid Yes Yes T5,T6,T14 Yes T5,T6,T14 INPUT
tl_o.a_ready Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
tl_o.d_error Yes Yes T76,T77,T139 Yes T76,T77,T139 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T77 Yes T76,T77,T139 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T6,*T14 Yes T5,T6,T14 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T79,T178,T179 Yes T79,T178,T179 INPUT
alert_rx_i[0].ping_n Yes Yes T79,T178,T82 Yes T79,T82,T180 INPUT
alert_rx_i[0].ping_p Yes Yes T79,T82,T180 Yes T79,T178,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T79,T178,T179 Yes T79,T178,T179 OUTPUT
cio_sck_i Yes Yes T5,T6,T14 Yes T5,T6,T7 INPUT
cio_csb_i Yes Yes T46,T5,T6 Yes T5,T6,T7 INPUT
cio_sd_o[3:0] Yes Yes T12,T181,T182 Yes T12,T181,T182 OUTPUT
cio_sd_en_o[3:0] Yes Yes T12,T181,T183 Yes T12,T181,T183 OUTPUT
cio_sd_i[3:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 INPUT
cio_tpm_csb_i Yes Yes T40,T41,T42 Yes T40,T41,T42 INPUT
passthrough_o.s_en[0] Yes Yes *T12,*T181,*T182 Yes T12,T181,T182 OUTPUT
passthrough_o.s_en[3:1] No No No OUTPUT
passthrough_o.s[3:0] Yes Yes T5,T6,T14 Yes T5,T6,T14 OUTPUT
passthrough_o.csb_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off.
passthrough_o.csb Yes Yes T46,T5,T6 Yes T5,T6,T7 OUTPUT
passthrough_o.sck_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off.
passthrough_o.sck Yes Yes T5,T6,T14 Yes T5,T6,T7 OUTPUT
passthrough_o.passthrough_en Yes Yes T183,T184,T185 Yes T12,T181,T182 OUTPUT
passthrough_i.s[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
intr_upload_cmdfifo_not_empty_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_upload_payload_not_empty_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_upload_payload_overflow_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_readbuf_watermark_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_readbuf_flip_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_tpm_header_not_empty_o Yes Yes T40,T142,T41 Yes T40,T142,T41 OUTPUT
intr_tpm_rdfifo_cmd_end_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
intr_tpm_rdfifo_drop_o Yes Yes T142,T143,T144 Yes T142,T143,T144 OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sck_monitor_o Yes Yes T5,T6,T14 Yes T5,T6,T7 OUTPUT
mbist_en_i Unreachable Unreachable Unreachable INPUT
scan_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%