Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.51	99.11	88.00	98.76		84.66	92.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.49	96.24	96.06	98.78		97.05	99.30

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_wkup_detect[0].u_pinmux_wkup	80.81	83.33	81.82			77.27
gen_wkup_detect[1].u_pinmux_wkup	60.10	66.67	45.45			68.18
gen_wkup_detect[2].u_pinmux_wkup	56.14	63.89	40.91			63.64
gen_wkup_detect[3].u_pinmux_wkup	79.29	83.33	77.27			77.27
gen_wkup_detect[4].u_pinmux_wkup	77.78	83.33	77.27			72.73
gen_wkup_detect[5].u_pinmux_wkup	80.81	83.33	81.82			77.27
gen_wkup_detect[6].u_pinmux_wkup	60.10	66.67	45.45			68.18
gen_wkup_detect[7].u_pinmux_wkup	80.81	83.33	81.82			77.27
u_pinmux_strap_sampling	98.82	99.62	95.65			100.00	100.00
u_reg	98.47	96.30	97.66			99.92	100.00
u_usbdev_aon_wake	98.43	100.00	95.59			98.11	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Line No.	Total	Covered	Percent
TOTAL		895	887	99.11
CONT_ASSIGN	133	1	1	100.00
ALWAYS	162	41	41	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	0	0.00
CONT_ASSIGN	244	1	0	0.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	248	0	0
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
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CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
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CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
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CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	312	0	0
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
ALWAYS	415	15	15	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	0	0.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	574	1	0	0.00
CONT_ASSIGN	574	1	0	0.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	574	1	0	0.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	578	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
133	1	1
162	1	1
163	1	1
164	1	1
167	1	1
168	1	1
169	1	1
			MISSING_ELSE
171	1	1
172	1	1
			MISSING_ELSE
174	1	1
175	1	1
			MISSING_ELSE
177	1	1
178	1	1
			MISSING_ELSE
180	1	1
181	1	1
			MISSING_ELSE
183	1	1
184	1	1
			MISSING_ELSE
186	1	1
187	1	1
			MISSING_ELSE
189	1	1
190	1	1
			MISSING_ELSE
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
198	1	1
199	1	1
			MISSING_ELSE
201	1	1
202	1	1
			MISSING_ELSE
204	1	1
205	1	1
			MISSING_ELSE
207	1	1
208	1	1
			MISSING_ELSE
210	1	1
211	1	1
			MISSING_ELSE
213	1	1
214	1	1
			MISSING_ELSE
216	1	1
217	1	1
			MISSING_ELSE
219	1	1
220	1	1
			MISSING_ELSE
222	1	1
223	1	1
			MISSING_ELSE
243	16	16
244	14	16
245		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
246		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
247		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
248		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
249	16	16
250	16	16
251	14	16
252	16	16
265	47	47
266	47	47
267		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
268		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
269		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
270		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
271	47	47
272	47	47
273	47	47
274	47	47
312		unreachable
313	1	1
412	1	1
415	1	1
416	1	1
417	1	1
418	1	1
419	1	1
420	1	1
422	1	1
425	1	1
426	1	1
427	1	1
428	1	1
			MISSING_ELSE
433	1	1
434	1	1
435	1	1
436	1	1
			MISSING_ELSE
452	1	1
456	57	57
466	1	1
467	1	1
471	47	47
475	47	47
484	47	47
488	47	47
493	47	47
495	47	47
503	1	1
507	16	16
511	16	16
520	15	16
524	16	16
529	16	16
531	16	16
543	1	1
548	1	1
553	8	8
574	5	8
578	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Total	Covered	Percent
Conditions	1975	1738	88.00
Logical	1975	1738	88.00
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
133-484	92.97
484-488	83.80
488	83.26
488-520	94.59
520-553	85.67

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Total	Covered	Percent
Totals	400	391	97.75
Total Bits	1940	1916	98.76
Total Bits 0->1	970	959	98.87
Total Bits 1->0	970	957	98.66

Ports	400	391	97.75
Port Bits	1940	1916	98.76
Port Bits 0->1	970	959	98.87
Port Bits 1->0	970	957	98.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T33,T34	Yes	T1,T2,T3	INPUT
rst_sys_ni	Yes	Yes	T2,T33,T34	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T2,T33,T34	Yes	T1,T2,T3	INPUT
pin_wkup_req_o	Yes	Yes	T27,T18,T19	Yes	T46,T27,T18	OUTPUT
usb_wkup_req_o	Yes	Yes	T18,T19,T58	Yes	T16,T18,T19	OUTPUT
sleep_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T62,T46	INPUT
strap_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
strap_en_override_i	Unreachable	Unreachable		Unreachable		INPUT
lc_dft_en_i[3:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T5,T6,T63	Yes	T5,T6,T63	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T2,T4,T64	Yes	T2,T4,T64	INPUT
pinmux_hw_debug_en_o[3:0]	Yes	Yes	T2,T33,T34	Yes	T1,T2,T3	OUTPUT
dft_strap_test_o.straps[1:0]	No	No		Yes	T65,T66,T67	OUTPUT
dft_strap_test_o.valid	Yes	Yes	T2,T33,T34	Yes	T1,T2,T3	OUTPUT
dft_hold_tap_sel_i	Unreachable	Unreachable		Unreachable		INPUT
lc_jtag_o.tdi	Yes	Yes	T48,T5,T6	Yes	T48,T5,T6	OUTPUT
lc_jtag_o.trst_n	Yes	Yes	T5,T6,T65	Yes	T48,T50,T68	OUTPUT
lc_jtag_o.tms	Yes	Yes	T48,T5,T6	Yes	T48,T5,T6	OUTPUT
lc_jtag_o.tck	Yes	Yes	T48,T5,T6	Yes	T48,T50,T68	OUTPUT
lc_jtag_i.tdo_oe	Yes	Yes	T48,T5,T6	Yes	T48,T5,T6	INPUT
lc_jtag_i.tdo	Yes	Yes	T48,T5,T6	Yes	T48,T5,T6	INPUT
rv_jtag_o.tdi	Yes	Yes	T49,T47,T5	Yes	T49,T47,T5	OUTPUT
rv_jtag_o.trst_n	Yes	Yes	T47,T5,T6	Yes	T49,T47,T5	OUTPUT
rv_jtag_o.tms	Yes	Yes	T49,T47,T5	Yes	T49,T47,T5	OUTPUT
rv_jtag_o.tck	Yes	Yes	T49,T47,T5	Yes	T49,T47,T5	OUTPUT
rv_jtag_i.tdo_oe	Yes	Yes	T49,T47,T5	Yes	T49,T47,T5	INPUT
rv_jtag_i.tdo	Yes	Yes	T49,T47,T5	Yes	T49,T47,T5	INPUT
dft_jtag_o.tdi	Yes	Yes	T65,T69,T70	Yes	T65,T69,T70	OUTPUT
dft_jtag_o.trst_n	Yes	Yes	T65,T69,T70	Yes	T65,T69,T70	OUTPUT
dft_jtag_o.tms	Yes	Yes	T65,T69,T70	Yes	T65,T69,T70	OUTPUT
dft_jtag_o.tck	Yes	Yes	T65,T69,T70	Yes	T65,T69,T70	OUTPUT
dft_jtag_i.tdo_oe	Yes	Yes	T65,T69,T71	Yes	T65,T69,T71	INPUT
dft_jtag_i.tdo	Yes	Yes	T65,T69,T71	Yes	T65,T69,T71	INPUT
usbdev_dppullup_en_i	Yes	Yes	T16,T18,T19	Yes	T16,T18,T19	INPUT
usbdev_dnpullup_en_i	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
usb_dppullup_en_o	Yes	Yes	T18,T19,T23	Yes	T16,T18,T19	OUTPUT
usb_dnpullup_en_o	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
usbdev_suspend_req_i	Yes	Yes	T16,T18,T19	Yes	T16,T18,T19	INPUT
usbdev_wake_ack_i	Yes	Yes	T16,T18,T19	Yes	T16,T18,T19	INPUT
usbdev_bus_not_idle_o	Yes	Yes	T18,T19,T58	Yes	T18,T19,T58	OUTPUT
usbdev_bus_reset_o	Yes	Yes	T73	Yes	T73	OUTPUT
usbdev_sense_lost_o	Yes	Yes	T18,T19,T58	Yes	T16,T18,T19	OUTPUT
usbdev_wake_detect_active_o	Yes	Yes	T18,T19,T58	Yes	T16,T18,T19	OUTPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[11:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:17]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T5,*T6	Yes	T49,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T78,T52,T24	Yes	T78,T52,T24	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T52,*T24,*T53	Yes	T52,T24,T53	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
periph_to_mio_i[74:0]	Yes	Yes	T15,T26,T27	Yes	T15,T26,T27	INPUT
periph_to_mio_oe_i[74:0]	Yes	Yes	T26,T28,T29	Yes	T15,T26,T27	INPUT
mio_to_periph_o[56:0]	Yes	Yes	T15,T26,T27	Yes	T15,T26,T27	OUTPUT
periph_to_dio_i[11:0]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T18,T19	INPUT
periph_to_dio_i[13:12]	No	No		No		INPUT
periph_to_dio_i[15:14]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
periph_to_dio_oe_i[15:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
dio_to_periph_o[15:0]	Yes	Yes	T7,T17,T23	Yes	T23,T24,T72	OUTPUT
mio_attr_o[0].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[0].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[0].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[0].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[0].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[0].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[1].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[1].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[1].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[1].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[1].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[2].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[2].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[2].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[2].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[2].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[3].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[3].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[3].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[3].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[3].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[4].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[4].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[4].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[4].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[4].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[5].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[5].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[5].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[5].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[5].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[6].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[6].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[6].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[6].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[6].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[7].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[7].pull_en	Yes	Yes	T30,T31,T32	Yes	T40,T41,T42	OUTPUT
mio_attr_o[7].pull_select	Yes	Yes	T30,T31,T32	Yes	T40,T41,T42	OUTPUT
mio_attr_o[7].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[7].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[8].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[8].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[8].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[8].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[8].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[9].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[9].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[9].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[9].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[9].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[10].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[10].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
mio_attr_o[10].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
mio_attr_o[10].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[10].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[11].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[11].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[11].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[11].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[11].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[12].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[12].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
mio_attr_o[12].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
mio_attr_o[12].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[12].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[13].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[13].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[13].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[13].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[13].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[14].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[14].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[14].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[14].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[14].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[15].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[15].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[15].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
mio_attr_o[15].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[15].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[16].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[16].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[16].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[16].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[16].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[17].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[17].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[17].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[17].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[17].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[18].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[18].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[18].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[18].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[18].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[19].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[19].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[19].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[19].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[19].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[20].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[20].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[20].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[20].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[20].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[21].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[21].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[21].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[21].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[21].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[22].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[22].pull_en	Yes	Yes	T30,T31,T32	Yes	T43,T44,T45	OUTPUT
mio_attr_o[22].pull_select	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
mio_attr_o[22].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[22].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[23].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[23].pull_en	Yes	Yes	T30,T31,T32	Yes	T43,T44,T45	OUTPUT
mio_attr_o[23].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[23].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[23].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[24].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[24].pull_en	Yes	Yes	T30,T31,T32	Yes	T43,T44,T45	OUTPUT
mio_attr_o[24].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[24].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[24].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[25].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[25].pull_en	Yes	Yes	T2,T33,T46	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].pull_select	Yes	Yes	T2,T33,T46	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[25].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[26].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[26].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[26].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[26].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[26].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[27].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[27].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[27].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[27].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[27].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[28].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[28].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[28].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[28].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[28].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[29].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[29].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[29].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[29].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[29].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[30].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[30].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[30].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[30].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[30].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[31].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[31].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[31].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[31].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[31].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[32].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[32].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[32].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[32].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[32].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[33].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[33].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[33].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[33].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[33].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[34].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[34].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[34].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[34].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[34].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[35].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[35].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[35].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[35].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[35].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[36].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[36].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[36].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[36].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[36].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[37].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[37].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[37].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[37].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[37].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[38].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[38].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[38].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[38].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[38].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[39].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[39].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[39].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[39].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[39].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[40].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[40].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[40].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[40].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[40].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[41].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[41].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[41].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[41].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[41].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[42].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[42].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[42].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[42].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[42].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[43].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[43].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[43].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[43].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[43].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[44].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[44].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[44].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[44].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[44].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[45].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[45].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[45].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[45].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[45].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[46].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[46].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[46].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[46].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
mio_attr_o[46].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_out_o[46:0]	Yes	Yes	T15,T26,T27	Yes	T7,T15,T26	OUTPUT
mio_oe_o[46:0]	Yes	Yes	T26,T28,T29	Yes	T7,T15,T26	OUTPUT
mio_in_i[46:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
dio_attr_o[0].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[0].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[0].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[0].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[0].keep_en	No	No		No		OUTPUT
dio_attr_o[0].schmitt_en	No	No		No		OUTPUT
dio_attr_o[0].od_en	No	No		No		OUTPUT
dio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[0].drive_strength[0]	Yes	Yes	*T2,*T33,*T34	Yes	T1,T2,T3	OUTPUT
dio_attr_o[0].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[1].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[1].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[1].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[1].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].drive_strength[0]	Yes	Yes	*T2,*T33,*T34	Yes	T1,T2,T3	OUTPUT
dio_attr_o[1].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[2].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[2].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
dio_attr_o[2].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
dio_attr_o[2].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[2].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[3].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[3].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
dio_attr_o[3].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
dio_attr_o[3].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[3].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[4].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[4].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
dio_attr_o[4].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
dio_attr_o[4].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[4].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[5].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[5].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
dio_attr_o[5].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T12	OUTPUT
dio_attr_o[5].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[5].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[6].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[6].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[6].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[6].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[6].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[7].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[7].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[7].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[7].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[7].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[8].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[8].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[8].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[8].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[8].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[9].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[9].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[9].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[9].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[9].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[10].virt_od_en	Yes	Yes	T30,T31,T36	Yes	T37,T38,T39	OUTPUT
dio_attr_o[10].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[10].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[10].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[10].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[11].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T37,T38,T39	OUTPUT
dio_attr_o[11].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[11].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[11].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[11].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[12].virt_od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[12].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[12].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].drive_strength[0]	No	No		No		OUTPUT
dio_attr_o[12].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[13].virt_od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].pull_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[13].pull_select	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[13].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].drive_strength[0]	No	No		No		OUTPUT
dio_attr_o[13].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[14].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[14].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
dio_attr_o[14].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
dio_attr_o[14].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[14].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].invert	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[15].virt_od_en	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[15].pull_en	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
dio_attr_o[15].pull_select	Yes	Yes	T30,T31,T32	Yes	T10,T11,T35	OUTPUT
dio_attr_o[15].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].drive_strength[0]	Yes	Yes	*T30,*T31,*T32	Yes	T30,T31,T32	OUTPUT
dio_attr_o[15].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_out_o[11:0]	Yes	Yes	*T7,*T16,*T17	Yes	T16,T18,T19	OUTPUT
dio_out_o[13:12]	No	No		No		OUTPUT
dio_out_o[15:14]	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	OUTPUT
dio_oe_o[15:0]	Yes	Yes	T23,T24,T25	Yes	T7,T23,T24	OUTPUT
dio_in_i[15:0]	Yes	Yes	T7,T17,T23	Yes	T23,T24,T72	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Line No.	Total	Covered	Percent
Branches		776	657	84.66
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	2	50.00
TERNARY	488	4	2	50.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	4	100.00
TERNARY	488	4	4	100.00
TERNARY	471	2	2	100.00
TERNARY	475	2	2	100.00
TERNARY	484	4	3	75.00
TERNARY	488	4	3	75.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	4	100.00
TERNARY	524	4	4	100.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	3	75.00
TERNARY	524	4	3	75.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	3	75.00
TERNARY	524	4	3	75.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	4	100.00
TERNARY	524	4	4	100.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	3	75.00
TERNARY	524	4	3	75.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	4	100.00
TERNARY	524	4	4	100.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	3	75.00
TERNARY	524	4	3	75.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	4	100.00
TERNARY	524	4	4	100.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	3	75.00
TERNARY	524	4	3	75.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	4	100.00
TERNARY	524	4	4	100.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	3	75.00
TERNARY	524	4	3	75.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	3	75.00
TERNARY	524	4	3	75.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	1	25.00
TERNARY	524	4	1	25.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	2	50.00
TERNARY	524	4	2	50.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	3	75.00
TERNARY	524	4	3	75.00
TERNARY	507	2	2	100.00
TERNARY	511	2	2	100.00
TERNARY	520	4	3	75.00
TERNARY	524	4	3	75.00
TERNARY	553	2	2	100.00
TERNARY	553	2	1	50.00
TERNARY	553	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	553	2	2	100.00
TERNARY	553	2	2	100.00
IF	162	2	2	100.00
IF	415	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T27,T8,T55
0	1	-	Covered	T7,T27,T55
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T27,T8,T55
0	1	-	Covered	T7,T27,T55
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T27,T53,T55
0	1	-	Covered	T7,T27,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T27,T53,T55
0	1	-	Covered	T7,T27,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T27,T52,T55
0	1	-	Covered	T53,T55,T56
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T27,T52,T55
0	1	-	Covered	T53,T55,T56
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T27,T55
0	1	-	Covered	T27,T55,T56
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T27,T55
0	1	-	Covered	T27,T55,T56
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T27,T55
0	1	-	Covered	T27,T53,T55
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T27,T55
0	1	-	Covered	T27,T53,T55
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T27,T52
0	1	-	Covered	T53,T55,T56
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T27,T52
0	1	-	Covered	T53,T55,T56
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T27,T52,T8
0	1	-	Covered	T7,T55,T56
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T27,T52,T8
0	1	-	Covered	T7,T55,T56
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T53,T55
0	1	-	Covered	T27,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T53,T55
0	1	-	Covered	T27,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T53
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T53
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T53,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T53,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T52,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T52,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T7,T52,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T7,T52,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T53,T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T53,T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[16].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[16].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[17].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[17].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[18].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[18].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T53,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T53,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[19].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[19].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[20].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[20].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[21].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[21].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Covered	T7,T52
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Covered	T7,T52
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[22].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[22].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[23].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[23].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T53,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T53,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[24].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[24].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[25].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[25].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[26].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[26].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T7,T53,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T7,T53,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[27].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[27].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T53,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T53,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[28].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[28].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[29].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[29].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[30].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[30].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T52,T53,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T52,T53,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[31].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[31].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[32].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[32].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[33].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[33].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[34].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[34].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T53,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T53,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[35].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[35].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[36].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[36].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Covered	T53
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Covered	T53
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[37].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[37].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[38].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[38].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[39].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[39].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Covered	T52
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Covered	T52
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[40].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[40].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[41].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[41].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T53,T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T53,T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[42].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[42].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[43].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[43].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T53,T8
0	1	-	Covered	T52,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T53,T8
0	1	-	Covered	T52,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[44].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[44].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[45].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[45].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	471	(reg2hw.mio_pad_sleep_status[46].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	475	(reg2hw.mio_pad_sleep_status[46].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? 
-2-:	484	((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? 
-3-:	484	((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T7,T53
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	488	((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? 
-2-:	488	((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? 
-3-:	488	((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T7,T53
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T52,T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T52,T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T53
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T53
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52,T53

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T52,T53,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T52,T53,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T53,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T53,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T52

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T52,T53
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T52,T53
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T53

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T52
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T52
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8,T9
0	1	-	Covered	T7,T53
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8,T9
0	1	-	Covered	T7,T53
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T52,T8
0	1	-	Covered	T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	507	(reg2hw.dio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	511	(reg2hw.dio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	520	((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	520	((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T52
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	524	((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	524	((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	524	((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T52
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	553	(reg2hw.wkup_detector[0].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T53
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(reg2hw.wkup_detector[1].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(reg2hw.wkup_detector[2].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(reg2hw.wkup_detector[3].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T54,T53
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(reg2hw.wkup_detector[4].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T52,T57
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(reg2hw.wkup_detector[5].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(reg2hw.wkup_detector[6].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	(reg2hw.wkup_detector[7].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Covered	T53
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	415	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	23	92.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	23	92.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	92151873	91555515	0	0
AonWkupReqKnownO_A	1250027	1088774	0	0
DftJtagTckKnown_A	92151873	91555515	0	0
DftJtagTmsKnown_A	92151873	91555515	0	0
DftJtagTrstKnown_A	92151873	91555515	0	0
DftStrapsKnown_A	92151873	91555515	0	0
DioKnownO_A	92151873	91555515	0	0
DioOeKnownO_A	92151873	91555515	0	0
FpvSecCmBusIntegrity_A	92151873	0	0	0
FpvSecCmRegWeOnehotCheck_A	92151873	4	0	0
LcJtagTckKnown_A	92151873	91555515	0	0
LcJtagTmsKnown_A	92151873	91555515	0	0
LcJtagTrstKnown_A	92151873	91555515	0	0
MioKnownO_A	92151873	91555515	0	0
MioOeKnownO_A	92151873	91555515	0	0
PinmuxWkupStable_A	1250027	3147	0	0
PwrMgrStrapSampleOnce0_A	92151873	1516	0	0
PwrMgrStrapSampleOnce1_A	92151873	0	0	857
RvJtagTckKnown_A	92151873	91555515	0	0
RvJtagTmsKnown_A	92151873	91555515	0	0
RvJtagTrstKnown_A	92151873	91555515	0	0
TlAReadyKnownO_A	92151873	91555515	0	0
TlDValidKnownO_A	92151873	91555515	0	0
UsbWakeDetectActiveKnownO_A	1250027	1088774	0	0
UsbWkupReqKnownO_A	1250027	1088774	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

AonWkupReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1250027	1088774	0	0
T1	534	371	0	0
T2	776	611	0	0
T3	4743	4581	0	0
T33	522	358	0	0
T34	731	568	0	0
T46	435	272	0	0
T62	1043	881	0	0
T83	346	184	0	0
T84	355	194	0	0
T85	623	461	0	0

DftJtagTckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

DftJtagTmsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

DftJtagTrstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

DftStrapsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

DioKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

DioOeKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

FpvSecCmBusIntegrity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	4	0	0
T18	178181	0	0	0
T27	25619	0	0	0
T81	66150	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	35761	0	0	0
T90	24764	0	0	0
T91	55999	0	0	0
T92	63281	0	0	0
T93	22202	0	0	0
T94	83181	0	0	0
T95	58480	0	0	0

LcJtagTckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

LcJtagTmsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

LcJtagTrstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

MioKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

MioOeKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

PinmuxWkupStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1250027	3147	0	0
T4	6562	0	0	0
T18	0	485	0	0
T19	0	419	0	0
T27	0	44	0	0
T34	731	0	0	0
T43	3346	0	0	0
T46	435	22	0	0
T48	397	0	0	0
T49	757	0	0	0
T54	0	22	0	0
T55	0	134	0	0
T57	0	22	0	0
T58	0	454	0	0
T85	623	0	0	0
T96	0	462	0	0
T97	0	478	0	0
T98	2417	0	0	0
T99	434	0	0	0
T100	484	0	0	0

PwrMgrStrapSampleOnce0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	1516	0	0
T1	38918	1	0	0
T2	56281	2	0	0
T3	548393	1	0	0
T33	35732	1	0	0
T34	41314	2	0	0
T46	23804	1	0	0
T62	48296	1	0	0
T83	22390	1	0	0
T84	21472	1	0	0
T85	40520	1	0	0

PwrMgrStrapSampleOnce1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	0	0	857

RvJtagTckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

RvJtagTmsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

RvJtagTrstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92151873	91555515	0	0
T1	38918	38316	0	0
T2	56281	55661	0	0
T3	548393	547672	0	0
T33	35732	35207	0	0
T34	41314	40836	0	0
T46	23804	23174	0	0
T62	48296	47881	0	0
T83	22390	21547	0	0
T84	21472	20850	0	0
T85	40520	40114	0	0

UsbWakeDetectActiveKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1250027	1088774	0	0
T1	534	371	0	0
T2	776	611	0	0
T3	4743	4581	0	0
T33	522	358	0	0
T34	731	568	0	0
T46	435	272	0	0
T62	1043	881	0	0
T83	346	184	0	0
T84	355	194	0	0
T85	623	461	0	0

UsbWkupReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1250027	1088774	0	0
T1	534	371	0	0
T2	776	611	0	0
T3	4743	4581	0	0
T33	522	358	0	0
T34	731	568	0	0
T46	435	272	0	0
T62	1043	881	0	0
T83	346	184	0	0
T84	355	194	0	0
T85	623	461	0	0