Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365066519	39086673	0	0
DepthKnown_A	365066519	364971820	0	0
RvalidKnown_A	365066519	364971820	0	0
WreadyKnown_A	365066519	364971820	0	0
gen_passthru_fifo.paramCheckPass	880	880	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	39086673	0	0
T1	142433	23469	0	0
T2	228838	22558	0	0
T3	143330	43472	0	0
T33	145163	17912	0	0
T34	167032	19276	0	0
T46	86752	11729	0	0
T62	186135	25573	0	0
T83	88237	9728	0	0
T84	85336	10921	0	0
T85	149918	24649	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365066519	29802593	0	0
DepthKnown_A	365066519	364971820	0	0
RvalidKnown_A	365066519	364971820	0	0
WreadyKnown_A	365066519	364971820	0	0
gen_passthru_fifo.paramCheckPass	880	880	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	29802593	0	0
T1	142433	16095	0	0
T2	228838	15549	0	0
T3	143330	39512	0	0
T33	145163	15499	0	0
T34	167032	13451	0	0
T46	86752	8034	0	0
T62	186135	18308	0	0
T83	88237	7724	0	0
T84	85336	7725	0	0
T85	149918	17309	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365066519	21867509	0	0
DepthKnown_A	365066519	364971820	0	0
RvalidKnown_A	365066519	364971820	0	0
WreadyKnown_A	365066519	364971820	0	0
gen_passthru_fifo.paramCheckPass	880	880	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	21867509	0	0
T1	142433	7838	0	0
T2	228838	10555	0	0
T3	143330	33076	0	0
T33	145163	5440	0	0
T34	167032	10921	0	0
T46	86752	5274	0	0
T62	186135	11858	0	0
T83	88237	5736	0	0
T84	85336	4577	0	0
T85	149918	8724	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	365066519	21365098	0	0
DepthKnown_A	365066519	364971820	0	0
RvalidKnown_A	365066519	364971820	0	0
WreadyKnown_A	365066519	364971820	0	0
gen_passthru_fifo.paramCheckPass	880	880	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	21365098	0	0
T1	142433	7559	0	0
T2	228838	10213	0	0
T3	143330	32907	0	0
T33	145163	5271	0	0
T34	167032	10550	0	0
T46	86752	5103	0	0
T62	186135	11470	0	0
T83	88237	5615	0	0
T84	85336	4429	0	0
T85	149918	8450	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	364971820	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441801796	90579	0	0
DepthKnown_A	441801796	441695236	0	0
RvalidKnown_A	441801796	441695236	0	0
WreadyKnown_A	441801796	441695236	0	0
gen_passthru_fifo.paramCheckPass	2770	2770	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	90579	0	0
T1	142433	26	0	0
T2	228838	102	0	0
T3	143330	29	0	0
T33	145163	47	0	0
T34	167032	104	0	0
T46	86752	24	0	0
T62	186135	40	0	0
T83	88237	13	0	0
T84	85336	20	0	0
T85	149918	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770	2770	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441801796	93276	0	0
DepthKnown_A	441801796	441695236	0	0
RvalidKnown_A	441801796	441695236	0	0
WreadyKnown_A	441801796	441695236	0	0
gen_passthru_fifo.paramCheckPass	2770	2770	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	93276	0	0
T1	142433	26	0	0
T2	228838	102	0	0
T3	143330	29	0	0
T33	145163	47	0	0
T34	167032	104	0	0
T46	86752	24	0	0
T62	186135	40	0	0
T83	88237	13	0	0
T84	85336	20	0	0
T85	149918	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770	2770	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441801796	48942	0	0
DepthKnown_A	441801796	441695236	0	0
RvalidKnown_A	441801796	441695236	0	0
WreadyKnown_A	441801796	441695236	0	0
gen_passthru_fifo.paramCheckPass	2770	2770	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	48942	0	0
T1	142433	23	0	0
T2	228838	94	0	0
T3	143330	28	0	0
T33	145163	46	0	0
T34	167032	98	0	0
T46	86752	21	0	0
T62	186135	34	0	0
T83	88237	12	0	0
T84	85336	19	0	0
T85	149918	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770	2770	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441801796	48942	0	0
DepthKnown_A	441801796	441695236	0	0
RvalidKnown_A	441801796	441695236	0	0
WreadyKnown_A	441801796	441695236	0	0
gen_passthru_fifo.paramCheckPass	2770	2770	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	48942	0	0
T1	142433	23	0	0
T2	228838	94	0	0
T3	143330	28	0	0
T33	145163	46	0	0
T34	167032	98	0	0
T46	86752	21	0	0
T62	186135	34	0	0
T83	88237	12	0	0
T84	85336	19	0	0
T85	149918	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770	2770	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441801796	41637	0	0
DepthKnown_A	441801796	441695236	0	0
RvalidKnown_A	441801796	441695236	0	0
WreadyKnown_A	441801796	441695236	0	0
gen_passthru_fifo.paramCheckPass	2770	2770	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	41637	0	0
T1	142433	3	0	0
T2	228838	8	0	0
T3	143330	1	0	0
T33	145163	1	0	0
T34	167032	6	0	0
T46	86752	3	0	0
T62	186135	6	0	0
T83	88237	1	0	0
T84	85336	1	0	0
T85	149918	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770	2770	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441801796	44334	0	0
DepthKnown_A	441801796	441695236	0	0
RvalidKnown_A	441801796	441695236	0	0
WreadyKnown_A	441801796	441695236	0	0
gen_passthru_fifo.paramCheckPass	2770	2770	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	44334	0	0
T1	142433	3	0	0
T2	228838	8	0	0
T3	143330	1	0	0
T33	145163	1	0	0
T34	167032	6	0	0
T46	86752	3	0	0
T62	186135	6	0	0
T83	88237	1	0	0
T84	85336	1	0	0
T85	149918	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441801796	441695236	0	0
T1	142433	142371	0	0
T2	228838	228721	0	0
T3	143330	143324	0	0
T33	145163	145039	0	0
T34	167032	166922	0	0
T46	86752	86690	0	0
T62	186135	186030	0	0
T83	88237	88186	0	0
T84	85336	85281	0	0
T85	149918	149867	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2770	2770	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0