Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : aon_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_aon_timer_aon 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_aon_timer_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.46 92.83 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : aon_timer
TotalCoveredPercent
Totals 38 38 100.00
Total Bits 314 314 100.00
Total Bits 0->1 157 157 100.00
Total Bits 1->0 157 157 100.00

Ports 38 38 100.00
Port Bits 314 314 100.00
Port Bits 0->1 157 157 100.00
Port Bits 1->0 157 157 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T33,T34 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T2,T33,T34 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T85 Yes T1,T2,T85 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T85 Yes T1,T2,T85 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T49,*T5,*T6 Yes T49,T5,T6 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T78,T52,T24 Yes T78,T52,T24 INPUT
tl_i.a_valid Yes Yes T1,T2,T85 Yes T1,T2,T85 INPUT
tl_o.a_ready Yes Yes T1,T2,T85 Yes T1,T2,T85 OUTPUT
tl_o.d_error Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T85 Yes T1,T2,T85 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T85 Yes T1,T2,T85 OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T85 Yes T1,T2,T85 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[5:0] Yes Yes *T76,*T77,*T139 Yes T75,T76,T77 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T85 Yes T1,T2,T85 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T85 Yes T1,T2,T85 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T79,T316,T80 Yes T79,T316,T80 INPUT
alert_rx_i[0].ping_n Yes Yes T79,T80,T82 Yes T79,T80,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T79,T80,T82 Yes T79,T80,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T79,T316,T80 Yes T79,T316,T80 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T2,T4,T64 Yes T2,T4,T64 INPUT
intr_wkup_timer_expired_o Yes Yes T1,T85,T244 Yes T1,T85,T244 OUTPUT
intr_wdog_timer_bark_o Yes Yes T4,T217,T218 Yes T4,T217,T218 OUTPUT
nmi_wdog_timer_bark_o Yes Yes T4,T217,T218 Yes T4,T217,T218 OUTPUT
wkup_req_o Yes Yes T1,T85,T4 Yes T1,T85,T4 OUTPUT
aon_timer_rst_req_o Yes Yes T4,T217,T218 Yes T4,T217,T218 OUTPUT
sleep_mode_i Yes Yes T1,T2,T3 Yes T1,T62,T46 INPUT

*Tests covering at least one bit in the range
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