Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T98,T43,T47	Yes	T98,T43,T47	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T98,T43,T47	Yes	T98,T43,T47	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T5,*T6	Yes	T49,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T78,T52,T24	Yes	T78,T52,T24	INPUT
tl_i.a_valid	Yes	Yes	T98,T43,T47	Yes	T98,T43,T47	INPUT
tl_o.a_ready	Yes	Yes	T98,T43,T271	Yes	T98,T43,T271	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T98,T271,T272	Yes	T98,T271,T272	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T98,T271,T272	Yes	T98,T43,T271	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T98,T271,T272	Yes	T98,T43,T271	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T24,*T53,*T75	Yes	T24,T53,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T98,*T271,*T272	Yes	T98,T271,T272	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T98,T43,T271	Yes	T98,T43,T271	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T674,T146	Yes	T79,T674,T146	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T674,T146	Yes	T79,T674,T146	OUTPUT
cio_rx_i	Yes	Yes	T2,T33,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T98,T271,T272	Yes	T98,T271,T272	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T98,T271,T272	Yes	T98,T271,T272	OUTPUT
intr_rx_watermark_o	Yes	Yes	T98,T271,T272	Yes	T98,T271,T272	OUTPUT
intr_tx_empty_o	Yes	Yes	T98,T271,T272	Yes	T98,T271,T272	OUTPUT
intr_rx_overflow_o	Yes	Yes	T98,T271,T272	Yes	T98,T271,T272	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T43,T47,T271	Yes	T43,T47,T271	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T43,T47,T271	Yes	T43,T47,T271	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T5,*T6	Yes	T49,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T78,T52,T24	Yes	T78,T52,T24	INPUT
tl_i.a_valid	Yes	Yes	T43,T47,T271	Yes	T43,T47,T271	INPUT
tl_o.a_ready	Yes	Yes	T43,T271,T272	Yes	T43,T271,T272	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T271,T272,T255	Yes	T271,T272,T255	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T271,T272,T255	Yes	T43,T271,T272	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T271,T272,T255	Yes	T43,T271,T272	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T24,*T53,*T75	Yes	T24,T53,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T271,*T272,*T255	Yes	T271,T272,T255	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T43,T271,T272	Yes	T43,T271,T272	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T146,T82	Yes	T79,T146,T82	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T82,T685	Yes	T79,T82,T145	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T82,T145	Yes	T79,T82,T685	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T146,T82	Yes	T79,T146,T82	OUTPUT
cio_rx_i	Yes	Yes	T2,T33,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T271,T272,T255	Yes	T271,T272,T255	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T271,T272,T255	Yes	T271,T272,T255	OUTPUT
intr_rx_watermark_o	Yes	Yes	T271,T272,T255	Yes	T271,T272,T255	OUTPUT
intr_tx_empty_o	Yes	Yes	T271,T272,T255	Yes	T271,T272,T255	OUTPUT
intr_rx_overflow_o	Yes	Yes	T271,T272,T255	Yes	T271,T272,T255	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T5,*T6	Yes	T49,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T78,T52,T24	Yes	T78,T52,T24	INPUT
tl_i.a_valid	Yes	Yes	T98,T267,T146	Yes	T98,T267,T146	INPUT
tl_o.a_ready	Yes	Yes	T98,T267,T146	Yes	T98,T267,T146	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T98,T267,T146	Yes	T98,T267,T146	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T98,T267,T146	Yes	T98,T267,T146	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T76,T77,T139	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T24,*T53,*T76	Yes	T24,T53,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T76,T77,T139	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T98,*T267,*T268	Yes	T98,T267,T268	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T98,T267,T146	Yes	T98,T267,T146	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T674,T146	Yes	T79,T674,T146	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T674,T146	Yes	T79,T674,T146	OUTPUT
cio_rx_i	Yes	Yes	T98,T267,T268	Yes	T98,T10,T7	INPUT
cio_tx_o	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	OUTPUT
intr_rx_watermark_o	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	OUTPUT
intr_tx_empty_o	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	OUTPUT
intr_rx_overflow_o	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T177,T307,T91	Yes	T177,T307,T91	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T177,T307,T91	Yes	T177,T307,T91	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T5,*T6	Yes	T49,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T78,T52,T24	Yes	T78,T52,T24	INPUT
tl_i.a_valid	Yes	Yes	T177,T146,T307	Yes	T177,T146,T307	INPUT
tl_o.a_ready	Yes	Yes	T177,T146,T307	Yes	T177,T146,T307	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T177,T307,T91	Yes	T177,T307,T91	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T177,T146,T307	Yes	T177,T146,T307	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T177,T146,T307	Yes	T177,T146,T307	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T76,T77,T139	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T24,*T53,*T75	Yes	T24,T53,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T139	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T177,*T307,*T91	Yes	T177,T307,T91	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T177,T146,T307	Yes	T177,T146,T307	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T146,T80	Yes	T79,T146,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T146,T80	Yes	T79,T146,T80	OUTPUT
cio_rx_i	Yes	Yes	T177,T307,T91	Yes	T177,T307,T91	INPUT
cio_tx_o	Yes	Yes	T177,T307,T91	Yes	T177,T307,T91	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T177,T307,T91	Yes	T177,T307,T91	OUTPUT
intr_rx_watermark_o	Yes	Yes	T177,T307,T91	Yes	T177,T307,T91	OUTPUT
intr_tx_empty_o	Yes	Yes	T177,T307,T91	Yes	T177,T307,T91	OUTPUT
intr_rx_overflow_o	Yes	Yes	T177,T307,T91	Yes	T177,T307,T91	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T13,T14,T294	Yes	T13,T14,T294	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T13,T14,T294	Yes	T13,T14,T294	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T5,*T6	Yes	T49,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T78,T52,T24	Yes	T78,T52,T24	INPUT
tl_i.a_valid	Yes	Yes	T13,T14,T146	Yes	T13,T14,T146	INPUT
tl_o.a_ready	Yes	Yes	T13,T14,T146	Yes	T13,T14,T146	OUTPUT
tl_o.d_error	Yes	Yes	T75,T77,T139	Yes	T75,T77,T139	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T14,T294	Yes	T13,T14,T294	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T13,T14,T146	Yes	T13,T14,T146	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T13,T14,T146	Yes	T13,T14,T146	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T24,*T53,*T75	Yes	T24,T53,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T13,*T14,*T294	Yes	T13,T14,T294	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T13,T14,T146	Yes	T13,T14,T146	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T146,T675	Yes	T79,T146,T675	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T146,T675	Yes	T79,T146,T675	OUTPUT
cio_rx_i	Yes	Yes	T13,T14,T294	Yes	T13,T14,T294	INPUT
cio_tx_o	Yes	Yes	T13,T14,T294	Yes	T13,T14,T294	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T13,T14,T294	Yes	T13,T14,T294	OUTPUT
intr_rx_watermark_o	Yes	Yes	T13,T14,T294	Yes	T13,T14,T294	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T14,T294	Yes	T13,T14,T294	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T14,T294	Yes	T13,T14,T294	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T292,T302,T303	Yes	T292,T302,T303	OUTPUT

*Tests covering at least one bit in the range