Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.54	96.47	89.29	98.77		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	90.79	96.47	89.29	100.00		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.79	96.47	89.29	100.00		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.58	97.59	95.86	98.65		98.66	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.51			96.51
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	99.24	98.69	98.69			99.58	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T201,T202
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T203,T204
1	0	Covered	T47,T5,T205

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T47,T5

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T146,T206
1	0	Covered	T1,T2,T3
1	1	Covered	T59,T60,T61

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T59,T60
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T146,T206

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T146,T206
1	0	Covered	T1,T2,T3
1	1	Covered	T52,T53,T59

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T146,T206
1	0	Covered	T1,T2,T3
1	1	Covered	T52,T53,T59

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T47,T5
0	1	0	Covered	T34,T201,T202
1	0	0	Covered	T207,T208,T209

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T62
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	117	96.69
Total Bits	1624	1604	98.77
Total Bits 0->1	812	802	98.77
Total Bits 1->0	812	802	98.77

Ports	121	117	96.69
Port Bits	1624	1604	98.77
Port Bits 0->1	812	802	98.77
Port Bits 1->0	812	802	98.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T75,T77,T210	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T49,T100,T64	Yes	T49,T100,T64	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T100,T64	Yes	T49,T100,T64	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T78,T52,T24	Yes	T78,T52,T24	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T78,T211,T75	Yes	T78,T211,T75	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T78,T211,T75	Yes	T78,T211,T75	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T78,T211,T75	Yes	T78,T211,T75	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T2,T49,T4	Yes	T2,T49,T4	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	INPUT
irq_timer_i	Yes	Yes	T215,T216,T142	Yes	T215,T216,T142	INPUT
irq_external_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T85	Yes	T1,T2,T85	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T85	Yes	T1,T2,T85	INPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T85	Yes	T1,T2,T85	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T85	Yes	T1,T2,T85	OUTPUT
nmi_wdog_i	Yes	Yes	T4,T217,T218	Yes	T4,T217,T218	INPUT
debug_req_i	Yes	Yes	T49,T219,T220	Yes	T49,T219,T220	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T62	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T52,*T53,*T75	Yes	T52,T53,T75	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T52,T53,T75	Yes	T52,T53,T75	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T62	Yes	T1,T2,T62	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T62	Yes	T1,T2,T62	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T52,*T53,*T75	Yes	T52,T53,T75	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T2,T34,T49	Yes	T1,T2,T84	INPUT
edn_i.edn_fips	Yes	Yes	T115,T116,T106	Yes	T110,T115,T116	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T100,T163,T164	Yes	T100,T163,T164	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T2,T3,T62	Yes	T1,T2,T3	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T62	INPUT
icache_otp_key_i.ack	Yes	Yes	T100,T163,T164	Yes	T100,T163,T164	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T82,T59	Yes	T79,T82,T59	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T82,T145	Yes	T79,T82,T145	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T82,T145	Yes	T79,T82,T145	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T47,T79,T146	Yes	T47,T79,T146	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T79,T82,T145	Yes	T79,T82,T145	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T79,T82,T145	Yes	T79,T82,T145	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T2,T34,T79	Yes	T2,T34,T79	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T79,T82,T145	Yes	T79,T145,T221	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T79,T145,T221	Yes	T79,T82,T145	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T145	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T79,T80,T145	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T82,T59	Yes	T79,T82,T59	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T47,T79,T146	Yes	T47,T79,T146	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T2,T34,T79	Yes	T2,T34,T79	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T47,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T203,T204
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T62
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	365066519	5	0	0
FpvSecCmIbexFetchEnable1_A	365066519	22489376	0	62
FpvSecCmIbexFetchEnable2_A	365066519	58857350	0	54
FpvSecCmIbexFetchEnable3Rev_A	365066519	301842821	0	1756
FpvSecCmIbexFetchEnable3_A	365066519	301844512	0	1684
FpvSecCmIbexInstrIntgErrCheck_A	365066519	151	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	365066519	590	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	365066519	0	0	0
FpvSecCmIbexPcMismatchCheck_A	365066519	0	0	0
FpvSecCmIbexRfEccErrCheck_A	365066519	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	365066519	0	0	0
FpvSecCmRegWeOnehotCheck_A	365066519	9	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	365066519	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	365066519	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	365066519	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	880	880	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	880	880	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	880	880	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	880	880	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	880	880	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	365066519	169	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	365066519	203	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	5	0	0
T2	228838	1	0	0
T3	143330	0	0	0
T33	145163	0	0	0
T34	167032	0	0	0
T46	86752	0	0	0
T62	186135	0	0	0
T83	88237	0	0	0
T84	85336	0	0	0
T85	149918	0	0	0
T98	111310	0	0	0
T203	0	1	0	0
T204	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	22489376	0	62
T1	142433	9927	0	0
T2	228838	41108	0	0
T3	143330	9919	0	0
T24	0	0	0	2
T33	145163	9967	0	2
T34	167032	19842	0	0
T46	86752	9927	0	0
T48	0	0	0	2
T52	0	0	0	2
T62	186135	19850	0	0
T78	0	0	0	2
T83	88237	9919	0	0
T84	85336	9919	0	0
T85	149918	9923	0	0
T150	0	0	0	2
T157	0	0	0	2
T159	0	0	0	2
T160	0	0	0	2
T224	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	58857350	0	54
T1	142433	38307	0	0
T2	228838	69555	0	0
T3	143330	34775	0	0
T24	0	0	0	2
T33	145163	34820	0	2
T34	167032	69550	0	0
T46	86752	36786	0	0
T52	0	0	0	2
T62	186135	71076	0	0
T78	0	0	0	2
T83	88237	34775	0	0
T84	85336	34775	0	0
T85	149918	37807	0	0
T157	0	0	0	2
T159	0	0	0	2
T160	0	0	0	2
T211	0	0	0	2
T225	0	0	0	2
T226	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	301842821	0	1756
T1	142433	104059	0	2
T2	228838	97903	0	2
T3	143330	139846	0	2
T33	145163	110214	0	2
T34	167032	97367	0	2
T46	86752	49900	0	2
T62	186135	114947	0	2
T83	88237	53408	0	2
T84	85336	50503	0	2
T85	149918	112056	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	301844512	0	1684
T1	142433	104062	0	2
T2	228838	97905	0	2
T3	143330	139846	0	2
T33	145163	110215	0	0
T34	167032	97368	0	2
T46	86752	49902	0	2
T62	186135	114950	0	2
T83	88237	53409	0	2
T84	85336	50504	0	2
T85	149918	112058	0	2
T98	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	151	0	0
T227	300267	75	0	0
T228	0	76	0	0
T229	253380	0	0	0
T230	87710	0	0	0
T231	91529	0	0	0
T232	69480	0	0	0
T233	206292	0	0	0
T234	154261	0	0	0
T235	127651	0	0	0
T236	84914	0	0	0
T237	236992	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	590	0	0
T4	137215	0	0	0
T10	83800	0	0	0
T34	167032	32	0	0
T43	155213	0	0	0
T48	35744	0	0	0
T49	197922	0	0	0
T98	111310	0	0	0
T99	84494	0	0	0
T100	74035	0	0	0
T161	0	31	0	0
T201	0	1	0	0
T202	0	99	0	0
T238	0	1	0	0
T239	0	32	0	0
T240	0	32	0	0
T241	0	32	0	0
T242	0	100	0	0
T243	0	32	0	0
T244	125716	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	9	0	0
T15	90815	0	0	0
T138	150758	0	0	0
T207	131801	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0
T251	110614	0	0	0
T252	249952	0	0	0
T253	281210	0	0	0
T254	607980	0	0	0
T255	229399	0	0	0
T256	73789	0	0	0
T257	101966	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	169	0	0
T4	137215	0	0	0
T10	83800	0	0	0
T20	104191	0	0	0
T50	200472	0	0	0
T68	188333	0	0	0
T100	74035	16	0	0
T117	71838	0	0	0
T141	224103	0	0	0
T163	0	16	0	0
T164	0	48	0	0
T244	125716	0	0	0
T258	0	16	0	0
T259	0	39	0	0
T260	0	34	0	0
T261	306149	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	203	0	0
T4	137215	0	0	0
T10	83800	0	0	0
T20	104191	0	0	0
T50	200472	0	0	0
T68	188333	0	0	0
T100	74035	42	0	0
T117	71838	0	0	0
T141	224103	0	0	0
T163	0	42	0	0
T164	0	12	0	0
T244	125716	0	0	0
T258	0	42	0	0
T259	0	9	0	0
T260	0	8	0	0
T261	306149	0	0	0
T262	0	16	0	0
T263	0	16	0	0
T264	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T201,T202
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T203,T204
1	0	Covered	T47,T5,T205

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T47,T5

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T146,T206
1	0	Covered	T1,T2,T3
1	1	Covered	T59,T60,T61

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T59,T60
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T146,T206

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T146,T206
1	0	Covered	T1,T2,T3
1	1	Covered	T52,T53,T59

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T146,T206
1	0	Covered	T1,T2,T3
1	1	Covered	T52,T53,T59

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T47,T5
0	1	0	Covered	T34,T201,T202
1	0	0	Covered	T207,T208,T209

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T62
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	117	100.00
Total Bits	1604	1604	100.00
Total Bits 0->1	802	802	100.00
Total Bits 1->0	802	802	100.00

Ports	117	117	100.00
Port Bits	1604	1604	100.00
Port Bits 0->1	802	802	100.00
Port Bits 1->0	802	802	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T75,T77,T210	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T49,T100,T64	Yes	T49,T100,T64	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T100,T64	Yes	T49,T100,T64	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T78,T52,T24	Yes	T78,T52,T24	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T78,T211,T75	Yes	T78,T211,T75	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T78,T211,T75	Yes	T78,T211,T75	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T78,T211,T75	Yes	T78,T211,T75	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T2,T49,T4	Yes	T2,T49,T4	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	INPUT
irq_timer_i	Yes	Yes	T215,T216,T142	Yes	T215,T216,T142	INPUT
irq_external_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T85	Yes	T1,T2,T85	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T85	Yes	T1,T2,T85	INPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T85	Yes	T1,T2,T85	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T85	Yes	T1,T2,T85	OUTPUT
nmi_wdog_i	Yes	Yes	T4,T217,T218	Yes	T4,T217,T218	INPUT
debug_req_i	Yes	Yes	T49,T219,T220	Yes	T49,T219,T220	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T62	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T52,*T53,*T75	Yes	T52,T53,T75	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T52,T53,T75	Yes	T52,T53,T75	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T62	Yes	T1,T2,T62	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T62	Yes	T1,T2,T62	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T52,*T53,*T75	Yes	T52,T53,T75	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T2,T34,T49	Yes	T1,T2,T84	INPUT
edn_i.edn_fips	Yes	Yes	T115,T116,T106	Yes	T110,T115,T116	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T100,T163,T164	Yes	T100,T163,T164	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T2,T3,T62	Yes	T1,T2,T3	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T62	INPUT
icache_otp_key_i.ack	Yes	Yes	T100,T163,T164	Yes	T100,T163,T164	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T82,T59	Yes	T79,T82,T59	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T82,T145	Yes	T79,T82,T145	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T82,T145	Yes	T79,T82,T145	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T47,T79,T146	Yes	T47,T79,T146	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T79,T82,T145	Yes	T79,T82,T145	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T79,T82,T145	Yes	T79,T82,T145	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T2,T34,T79	Yes	T2,T34,T79	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T79,T82,T145	Yes	T79,T145,T221	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T79,T145,T221	Yes	T79,T82,T145	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T145	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T79,T80,T145	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T82,T59	Yes	T79,T82,T59	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T47,T79,T146	Yes	T47,T79,T146	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T2,T34,T79	Yes	T2,T34,T79	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T47,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T203,T204
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T62
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	365066519	5	0	0
FpvSecCmIbexFetchEnable1_A	365066519	22489376	0	62
FpvSecCmIbexFetchEnable2_A	365066519	58857350	0	54
FpvSecCmIbexFetchEnable3Rev_A	365066519	301842821	0	1756
FpvSecCmIbexFetchEnable3_A	365066519	301844512	0	1684
FpvSecCmIbexInstrIntgErrCheck_A	365066519	151	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	365066519	590	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	365066519	0	0	0
FpvSecCmIbexPcMismatchCheck_A	365066519	0	0	0
FpvSecCmIbexRfEccErrCheck_A	365066519	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	365066519	0	0	0
FpvSecCmRegWeOnehotCheck_A	365066519	9	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	365066519	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	365066519	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	365066519	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	880	880	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	880	880	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	880	880	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	880	880	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	880	880	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	365066519	169	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	365066519	203	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	5	0	0
T2	228838	1	0	0
T3	143330	0	0	0
T33	145163	0	0	0
T34	167032	0	0	0
T46	86752	0	0	0
T62	186135	0	0	0
T83	88237	0	0	0
T84	85336	0	0	0
T85	149918	0	0	0
T98	111310	0	0	0
T203	0	1	0	0
T204	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	22489376	0	62
T1	142433	9927	0	0
T2	228838	41108	0	0
T3	143330	9919	0	0
T24	0	0	0	2
T33	145163	9967	0	2
T34	167032	19842	0	0
T46	86752	9927	0	0
T48	0	0	0	2
T52	0	0	0	2
T62	186135	19850	0	0
T78	0	0	0	2
T83	88237	9919	0	0
T84	85336	9919	0	0
T85	149918	9923	0	0
T150	0	0	0	2
T157	0	0	0	2
T159	0	0	0	2
T160	0	0	0	2
T224	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	58857350	0	54
T1	142433	38307	0	0
T2	228838	69555	0	0
T3	143330	34775	0	0
T24	0	0	0	2
T33	145163	34820	0	2
T34	167032	69550	0	0
T46	86752	36786	0	0
T52	0	0	0	2
T62	186135	71076	0	0
T78	0	0	0	2
T83	88237	34775	0	0
T84	85336	34775	0	0
T85	149918	37807	0	0
T157	0	0	0	2
T159	0	0	0	2
T160	0	0	0	2
T211	0	0	0	2
T225	0	0	0	2
T226	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	301842821	0	1756
T1	142433	104059	0	2
T2	228838	97903	0	2
T3	143330	139846	0	2
T33	145163	110214	0	2
T34	167032	97367	0	2
T46	86752	49900	0	2
T62	186135	114947	0	2
T83	88237	53408	0	2
T84	85336	50503	0	2
T85	149918	112056	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	301844512	0	1684
T1	142433	104062	0	2
T2	228838	97905	0	2
T3	143330	139846	0	2
T33	145163	110215	0	0
T34	167032	97368	0	2
T46	86752	49902	0	2
T62	186135	114950	0	2
T83	88237	53409	0	2
T84	85336	50504	0	2
T85	149918	112058	0	2
T98	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	151	0	0
T227	300267	75	0	0
T228	0	76	0	0
T229	253380	0	0	0
T230	87710	0	0	0
T231	91529	0	0	0
T232	69480	0	0	0
T233	206292	0	0	0
T234	154261	0	0	0
T235	127651	0	0	0
T236	84914	0	0	0
T237	236992	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	590	0	0
T4	137215	0	0	0
T10	83800	0	0	0
T34	167032	32	0	0
T43	155213	0	0	0
T48	35744	0	0	0
T49	197922	0	0	0
T98	111310	0	0	0
T99	84494	0	0	0
T100	74035	0	0	0
T161	0	31	0	0
T201	0	1	0	0
T202	0	99	0	0
T238	0	1	0	0
T239	0	32	0	0
T240	0	32	0	0
T241	0	32	0	0
T242	0	100	0	0
T243	0	32	0	0
T244	125716	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	9	0	0
T15	90815	0	0	0
T138	150758	0	0	0
T207	131801	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0
T251	110614	0	0	0
T252	249952	0	0	0
T253	281210	0	0	0
T254	607980	0	0	0
T255	229399	0	0	0
T256	73789	0	0	0
T257	101966	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	169	0	0
T4	137215	0	0	0
T10	83800	0	0	0
T20	104191	0	0	0
T50	200472	0	0	0
T68	188333	0	0	0
T100	74035	16	0	0
T117	71838	0	0	0
T141	224103	0	0	0
T163	0	16	0	0
T164	0	48	0	0
T244	125716	0	0	0
T258	0	16	0	0
T259	0	39	0	0
T260	0	34	0	0
T261	306149	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365066519	203	0	0
T4	137215	0	0	0
T10	83800	0	0	0
T20	104191	0	0	0
T50	200472	0	0	0
T68	188333	0	0	0
T100	74035	42	0	0
T117	71838	0	0	0
T141	224103	0	0	0
T163	0	42	0	0
T164	0	12	0	0
T244	125716	0	0	0
T258	0	42	0	0
T259	0	9	0	0
T260	0	8	0	0
T261	306149	0	0	0
T262	0	16	0	0
T263	0	16	0	0
T264	0	16	0	0