Unified Coverage Report :: Module Instance :: tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

Module Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[35].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[36].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[37].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[38].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[39].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[40].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[41].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[42].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[43].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[44].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[45].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[46].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T48,T49,T50
0	1	Covered	T48,T49,T47
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T15,T26,T28
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T15,T26,T28

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T15,T26,T28
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T26,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T15,T26,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T26,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T48,T49,T47
0	1	Covered	T48,T49,T47
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T48,T49,T47
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T48,T49,T47

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T48,T49,T47
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T48,T49,T47

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T48,T49,T47

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T48,T49,T47
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T48,T49,T50
0	1	Covered	T48,T49,T47
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T15,T26,T28
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T48,T49,T47
0	1	Covered	T48,T49,T50
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T48,T49,T50
0	1	Covered	T48,T49,T50
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T15,T26,T28
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T65,T7,T21
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T21,T15,T26
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T21,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T21,T15,T26
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T21,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T15,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T21,T15
0	1	Covered	T7,T21,T15
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T21,T15,T26
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T21,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T21,T15,T26
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T21,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T15,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T65,T7,T69
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T15,T26
0	1	Covered	T15,T26,T28
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T15,T26,T28
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T15,T26
0	1	Covered	T7,T15,T26
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T15,T26,T28
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T15,T26,T28

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T15,T26,T28
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T26,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T15,T26,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T26,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T15,T26,T78
0	1	Covered	T7,T15,T26
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T21,T252,T15
0	1	Covered	T7,T252,T15
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T32
1	0	Covered	T7,T15,T26
1	1	Covered	T30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T31,T32
1	1	Covered	T7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	(ie_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	880	880	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	880	880	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T46	1	1	0	0
T62	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0