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Module Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[35].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[36].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[37].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[38].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[39].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[40].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[41].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[42].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[43].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[44].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[45].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[46].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT48,T49,T50
01CoveredT48,T49,T47
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT15,T26,T28
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT15,T26,T28

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT15,T26,T28
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T26,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT15,T26,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T15,T26,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT48,T49,T47
01CoveredT48,T49,T47
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT48,T49,T47
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT48,T49,T47

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT48,T49,T47
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT48,T49,T47

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT48,T49,T47

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T48,T49,T47
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT48,T49,T50
01CoveredT48,T49,T47
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT15,T26,T28
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T15,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT48,T49,T47
01CoveredT48,T49,T50
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T15,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT48,T49,T50
01CoveredT48,T49,T50
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT15,T26,T28
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T15,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT65,T7,T21
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT21,T15,T26
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT21,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT21,T15,T26
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT21,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T15,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT7,T21,T15
01CoveredT7,T21,T15
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT21,T15,T26
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT21,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT21,T15,T26
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT21,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T15,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT65,T7,T69
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T15,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT7,T15,T26
01CoveredT15,T26,T28
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT15,T26,T28
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T15,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT7,T15,T26
01CoveredT7,T15,T26
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT15,T26,T28
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT15,T26,T28

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT15,T26,T28
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T26,T28

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT15,T26,T28

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T15,T26,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT15,T26,T78
01CoveredT7,T15,T26
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T15,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT21,T252,T15
01CoveredT7,T252,T15
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT30,T31,T32
01CoveredT1,T2,T3
10CoveredT30,T31,T32

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT30,T31,T32

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT7,T15,T26
11CoveredT30,T31,T32

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT30,T31,T32
11CoveredT7,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T7,T15,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 880 880 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%