Module Definition
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Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.83 99.34 100.00 100.00 100.00 u_pinmux_strap_sampling


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 880 880 0 0
OutputsKnown_A 92151873 91555619 0 0
gen_no_flops.OutputDelay_A 92151873 91555619 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 92151873 91555619 0 0
T1 38918 38316 0 0
T2 56281 55661 0 0
T3 548393 547672 0 0
T33 35732 35207 0 0
T34 41314 40836 0 0
T46 23804 23174 0 0
T62 48296 47881 0 0
T83 22390 21547 0 0
T84 21472 20850 0 0
T85 40520 40114 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 92151873 91555619 0 0
T1 38918 38316 0 0
T2 56281 55661 0 0
T3 548393 547672 0 0
T33 35732 35207 0 0
T34 41314 40836 0 0
T46 23804 23174 0 0
T62 48296 47881 0 0
T83 22390 21547 0 0
T84 21472 20850 0 0
T85 40520 40114 0 0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 880 880 0 0
OutputsKnown_A 92151873 91555619 0 0
gen_no_flops.OutputDelay_A 92151873 91555619 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 880 880 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T46 1 1 0 0
T62 1 1 0 0
T83 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 92151873 91555619 0 0
T1 38918 38316 0 0
T2 56281 55661 0 0
T3 548393 547672 0 0
T33 35732 35207 0 0
T34 41314 40836 0 0
T46 23804 23174 0 0
T62 48296 47881 0 0
T83 22390 21547 0 0
T84 21472 20850 0 0
T85 40520 40114 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 92151873 91555619 0 0
T1 38918 38316 0 0
T2 56281 55661 0 0
T3 548393 547672 0 0
T33 35732 35207 0 0
T34 41314 40836 0 0
T46 23804 23174 0 0
T62 48296 47881 0 0
T83 22390 21547 0 0
T84 21472 20850 0 0
T85 40520 40114 0 0

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