Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.63	76.19	100.00	95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	91.56	76.19	100.00	98.48

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	76.19	100.00	98.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.65	95.45	94.45	95.62		95.33	97.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	95.45	95.40	94.06	95.61		95.15	97.02
u_ast	94.79			94.79
u_padring	99.29	99.77	100.00	96.66		100.00	100.00
u_prim_usb_diff_rx	96.30	100.00	88.89			100.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		21	16	76.19
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	786	1	0	0.00
CONT_ASSIGN	797	1	0	0.00
CONT_ASSIGN	822	1	0	0.00
CONT_ASSIGN	829	1	0	0.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	851	1	0	0.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1040	1	1	100.00
CONT_ASSIGN	1041	1	1	100.00
CONT_ASSIGN	1042	1	1	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1050	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	1	1
213	1	1
786	0	1
797	0	1
822	0	1
829	0	1
836	1	1
839	1	1
845	1	1
847	1	1
851	0	1
854	1	1
1023	1	1
1040	1	1
1041	1	1
1042	1	1
1043	1	1
1047	1	1
1048	1	1
1049	1	1
1050	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T62,T46

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	70	64	91.43
Total Bits	140	134	95.71
Total Bits 0->1	70	70	100.00
Total Bits 1->0	70	64	91.43

Ports	70	64	91.43
Port Bits	140	134	95.71
Port Bits 0->1	70	70	100.00
Port Bits 1->0	70	64	91.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T7,T17,T23	Yes	T23,T24,T72	INOUT
USB_N	Yes	Yes	T23,T24,T72	Yes	T23,T24,T72	INOUT
CC1	No	No		Yes	T7,T8,T9	INOUT
CC2	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_VOLT	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_MODE0	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_MODE1	No	No		Yes	T7,T8,T9	INOUT
OTP_EXT_VOLT	No	No		Yes	T7,T8,T9	INOUT
SPI_HOST_D0	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_D1	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_D2	Yes	Yes	T12,T183,T184	Yes	T12,T183,T184	INOUT
SPI_HOST_D3	Yes	Yes	T12,T183,T184	Yes	T12,T183,T184	INOUT
SPI_HOST_CLK	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_CS_L	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INOUT
SPI_DEV_D0	Yes	Yes	T5,T6,T14	Yes	T5,T6,T14	INOUT
SPI_DEV_D1	Yes	Yes	T5,T6,T14	Yes	T5,T6,T14	INOUT
SPI_DEV_D2	Yes	Yes	T12,T183,T184	Yes	T12,T183,T8	INOUT
SPI_DEV_D3	Yes	Yes	T12,T183,T184	Yes	T12,T183,T184	INOUT
SPI_DEV_CLK	Yes	Yes	T5,T6,T14	Yes	T5,T6,T7	INOUT
SPI_DEV_CS_L	Yes	Yes	T46,T5,T6	Yes	T5,T6,T7	INOUT
IOR8	Yes	Yes	T20,T7,T21	Yes	T46,T20,T7	INOUT
IOR9	Yes	Yes	T20,T21,T252	Yes	T46,T20,T7	INOUT
IOA0	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INOUT
IOA1	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INOUT
IOA2	Yes	Yes	T15,T26,T27	Yes	T7,T15,T26	INOUT
IOA3	Yes	Yes	T15,T26,T27	Yes	T15,T26,T27	INOUT
IOA4	Yes	Yes	T177,T15,T26	Yes	T46,T177,T15	INOUT
IOA5	Yes	Yes	T177,T15,T26	Yes	T177,T15,T26	INOUT
IOA6	Yes	Yes	T15,T26,T27	Yes	T15,T26,T27	INOUT
IOA7	Yes	Yes	T15,T40,T265	Yes	T15,T40,T265	INOUT
IOA8	Yes	Yes	T15,T265,T266	Yes	T15,T265,T266	INOUT
IOB0	Yes	Yes	T35,T30,T31	Yes	T7,T35,T30	INOUT
IOB1	Yes	Yes	T35,T30,T31	Yes	T35,T30,T31	INOUT
IOB2	Yes	Yes	T30,T31,T32	Yes	T9,T30,T31	INOUT
IOB3	Yes	Yes	T20,T21,T252	Yes	T20,T7,T252	INOUT
IOB4	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	INOUT
IOB5	Yes	Yes	T98,T7,T267	Yes	T98,T267,T268	INOUT
IOB6	Yes	Yes	T20,T21,T252	Yes	T20,T252,T15	INOUT
IOB7	Yes	Yes	T15,T26,T18	Yes	T21,T15,T37	INOUT
IOB8	Yes	Yes	T20,T252,T15	Yes	T7,T252,T15	INOUT
IOB9	Yes	Yes	T20,T21,T15	Yes	T21,T15,T26	INOUT
IOB10	Yes	Yes	T15,T26,T269	Yes	T7,T15,T26	INOUT
IOB11	Yes	Yes	T15,T270,T26	Yes	T7,T15,T270	INOUT
IOB12	Yes	Yes	T15,T270,T26	Yes	T15,T270,T26	INOUT
IOC0	Yes	Yes	T43,T5,T6	Yes	T5,T6,T254	INOUT
IOC1	Yes	Yes	T5,T6,T14	Yes	T5,T6,T7	INOUT
IOC2	Yes	Yes	T5,T6,T14	Yes	T5,T6,T7	INOUT
IOC3	Yes	Yes	T271,T7,T272	Yes	T271,T272,T255	INOUT
IOC4	Yes	Yes	T271,T272,T255	Yes	T271,T272,T255	INOUT
IOC5	Yes	Yes	T5,T6,T65	Yes	T5,T6,T65	INOUT
IOC6	Yes	Yes	T50,T68,T114	Yes	T50,T68,T114	INOUT
IOC7	Yes	Yes	T20,T252,T273	Yes	T20,T7,T21	INOUT
IOC8	Yes	Yes	T65,T69,T71	Yes	T5,T6,T7	INOUT
IOC9	Yes	Yes	T20,T15,T273	Yes	T20,T21,T15	INOUT
IOC10	Yes	Yes	T15,T26,T269	Yes	T15,T26,T269	INOUT
IOC11	Yes	Yes	T15,T26,T269	Yes	T7,T15,T26	INOUT
IOC12	Yes	Yes	T15,T26,T269	Yes	T7,T15,T26	INOUT
IOR0	Yes	Yes	T48,T49,T47	Yes	T48,T49,T47	INOUT
IOR1	Yes	Yes	T48,T49,T47	Yes	T48,T49,T47	INOUT
IOR2	Yes	Yes	T48,T49,T47	Yes	T48,T49,T47	INOUT
IOR3	Yes	Yes	T48,T49,T47	Yes	T48,T49,T47	INOUT
IOR4	Yes	Yes	T47,T5,T6	Yes	T48,T49,T50	INOUT
IOR5	Yes	Yes	T21,T15,T26	Yes	T7,T21,T15	INOUT
IOR6	Yes	Yes	T15,T26,T28	Yes	T7,T21,T15	INOUT
IOR7	Yes	Yes	T15,T26,T28	Yes	T15,T26,T28	INOUT
IOR10	Yes	Yes	T15,T26,T28	Yes	T15,T26,T28	INOUT
IOR11	Yes	Yes	T15,T26,T28	Yes	T7,T15,T26	INOUT
IOR12	Yes	Yes	T15,T26,T28	Yes	T15,T26,T28	INOUT
IOR13	Yes	Yes	T252,T15,T274	Yes	T252,T15,T274	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		21	16	76.19
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	786	1	0	0.00
CONT_ASSIGN	797	1	0	0.00
CONT_ASSIGN	822	1	0	0.00
CONT_ASSIGN	829	1	0	0.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	847	1	1	100.00
CONT_ASSIGN	851	1	0	0.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	1023	1	1	100.00
CONT_ASSIGN	1040	1	1	100.00
CONT_ASSIGN	1041	1	1	100.00
CONT_ASSIGN	1042	1	1	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
CONT_ASSIGN	1050	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
212	1	1
213	1	1
786	0	1
797	0	1
822	0	1
829	0	1
836	1	1
839	1	1
845	1	1
847	1	1
851	0	1
854	1	1
1023	1	1
1040	1	1
1041	1	1
1042	1	1
1043	1	1
1047	1	1
1048	1	1
1049	1	1
1050	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T62,T46

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	66	64	96.97
Total Bits	132	130	98.48
Total Bits 0->1	66	66	100.00
Total Bits 1->0	66	64	96.97

Ports	66	64	96.97
Port Bits	132	130	98.48
Port Bits 0->1	66	66	100.00
Port Bits 1->0	66	64	96.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INOUT
USB_P	Yes	Yes	T7,T17,T23	Yes	T23,T24,T72	INOUT
USB_N	Yes	Yes	T23,T24,T72	Yes	T23,T24,T72	INOUT
CC1	No	No		Yes	T7,T8,T9	INOUT
CC2	No	No		Yes	T7,T8,T9	INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_D1	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_D2	Yes	Yes	T12,T183,T184	Yes	T12,T183,T184	INOUT
SPI_HOST_D3	Yes	Yes	T12,T183,T184	Yes	T12,T183,T184	INOUT
SPI_HOST_CLK	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INOUT
SPI_HOST_CS_L	Yes	Yes	T10,T11,T12	Yes	T10,T7,T11	INOUT
SPI_DEV_D0	Yes	Yes	T5,T6,T14	Yes	T5,T6,T14	INOUT
SPI_DEV_D1	Yes	Yes	T5,T6,T14	Yes	T5,T6,T14	INOUT
SPI_DEV_D2	Yes	Yes	T12,T183,T184	Yes	T12,T183,T8	INOUT
SPI_DEV_D3	Yes	Yes	T12,T183,T184	Yes	T12,T183,T184	INOUT
SPI_DEV_CLK	Yes	Yes	T5,T6,T14	Yes	T5,T6,T7	INOUT
SPI_DEV_CS_L	Yes	Yes	T46,T5,T6	Yes	T5,T6,T7	INOUT
IOR8	Yes	Yes	T20,T7,T21	Yes	T46,T20,T7	INOUT
IOR9	Yes	Yes	T20,T21,T252	Yes	T46,T20,T7	INOUT
IOA0	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INOUT
IOA1	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INOUT
IOA2	Yes	Yes	T15,T26,T27	Yes	T7,T15,T26	INOUT
IOA3	Yes	Yes	T15,T26,T27	Yes	T15,T26,T27	INOUT
IOA4	Yes	Yes	T177,T15,T26	Yes	T46,T177,T15	INOUT
IOA5	Yes	Yes	T177,T15,T26	Yes	T177,T15,T26	INOUT
IOA6	Yes	Yes	T15,T26,T27	Yes	T15,T26,T27	INOUT
IOA7	Yes	Yes	T15,T40,T265	Yes	T15,T40,T265	INOUT
IOA8	Yes	Yes	T15,T265,T266	Yes	T15,T265,T266	INOUT
IOB0	Yes	Yes	T35,T30,T31	Yes	T7,T35,T30	INOUT
IOB1	Yes	Yes	T35,T30,T31	Yes	T35,T30,T31	INOUT
IOB2	Yes	Yes	T30,T31,T32	Yes	T9,T30,T31	INOUT
IOB3	Yes	Yes	T20,T21,T252	Yes	T20,T7,T252	INOUT
IOB4	Yes	Yes	T98,T267,T268	Yes	T98,T267,T268	INOUT
IOB5	Yes	Yes	T98,T7,T267	Yes	T98,T267,T268	INOUT
IOB6	Yes	Yes	T20,T21,T252	Yes	T20,T252,T15	INOUT
IOB7	Yes	Yes	T15,T26,T18	Yes	T21,T15,T37	INOUT
IOB8	Yes	Yes	T20,T252,T15	Yes	T7,T252,T15	INOUT
IOB9	Yes	Yes	T20,T21,T15	Yes	T21,T15,T26	INOUT
IOB10	Yes	Yes	T15,T26,T269	Yes	T7,T15,T26	INOUT
IOB11	Yes	Yes	T15,T270,T26	Yes	T7,T15,T270	INOUT
IOB12	Yes	Yes	T15,T270,T26	Yes	T15,T270,T26	INOUT
IOC0	Yes	Yes	T43,T5,T6	Yes	T5,T6,T254	INOUT
IOC1	Yes	Yes	T5,T6,T14	Yes	T5,T6,T7	INOUT
IOC2	Yes	Yes	T5,T6,T14	Yes	T5,T6,T7	INOUT
IOC3	Yes	Yes	T271,T7,T272	Yes	T271,T272,T255	INOUT
IOC4	Yes	Yes	T271,T272,T255	Yes	T271,T272,T255	INOUT
IOC5	Yes	Yes	T5,T6,T65	Yes	T5,T6,T65	INOUT
IOC6	Yes	Yes	T50,T68,T114	Yes	T50,T68,T114	INOUT
IOC7	Yes	Yes	T20,T252,T273	Yes	T20,T7,T21	INOUT
IOC8	Yes	Yes	T65,T69,T71	Yes	T5,T6,T7	INOUT
IOC9	Yes	Yes	T20,T15,T273	Yes	T20,T21,T15	INOUT
IOC10	Yes	Yes	T15,T26,T269	Yes	T15,T26,T269	INOUT
IOC11	Yes	Yes	T15,T26,T269	Yes	T7,T15,T26	INOUT
IOC12	Yes	Yes	T15,T26,T269	Yes	T7,T15,T26	INOUT
IOR0	Yes	Yes	T48,T49,T47	Yes	T48,T49,T47	INOUT
IOR1	Yes	Yes	T48,T49,T47	Yes	T48,T49,T47	INOUT
IOR2	Yes	Yes	T48,T49,T47	Yes	T48,T49,T47	INOUT
IOR3	Yes	Yes	T48,T49,T47	Yes	T48,T49,T47	INOUT
IOR4	Yes	Yes	T47,T5,T6	Yes	T48,T49,T50	INOUT
IOR5	Yes	Yes	T21,T15,T26	Yes	T7,T21,T15	INOUT
IOR6	Yes	Yes	T15,T26,T28	Yes	T7,T21,T15	INOUT
IOR7	Yes	Yes	T15,T26,T28	Yes	T15,T26,T28	INOUT
IOR10	Yes	Yes	T15,T26,T28	Yes	T15,T26,T28	INOUT
IOR11	Yes	Yes	T15,T26,T28	Yes	T7,T15,T26	INOUT
IOR12	Yes	Yes	T15,T26,T28	Yes	T15,T26,T28	INOUT
IOR13	Yes	Yes	T252,T15,T274	Yes	T252,T15,T274	INOUT