Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3767661	1			T68	139		T69	464		T70	497
values[2]	755936	1			T68	58		T69	111		T70	38
values[3]	106655	1			T70	2		T76	3		T75	207
values[4]	56514	1			T75	118		T412	11		T503	11
values[5]	39342	1			T75	74		T412	9		T413	129
values[6]	29453	1			T75	69		T412	6		T413	88
values[7]	24034	1			T75	63		T412	14		T413	49
values[8]	20190	1			T75	46		T412	11		T413	71
values[9]	17997	1			T75	44		T412	8		T413	57
values[10]	16600	1			T75	52		T412	3		T413	58
values[11]	15110	1			T75	19		T413	42		T741	3
values[12]	14249	1			T413	53		T741	3		T398	39
values[13]	13738	1			T413	59		T741	3		T398	79
values[14]	12900	1			T413	56		T741	3		T398	51
values[15]	12527	1			T413	51		T741	3		T398	38
values[16]	11934	1			T413	42		T741	3		T398	38
values[17]	11750	1			T413	33		T741	3		T398	36
values[18]	11484	1			T413	29		T741	3		T398	22
values[19]	11038	1			T413	28		T741	3		T398	24
values[20]	10473	1			T413	22		T741	3		T398	16
values[21]	10103	1			T413	18		T741	3		T398	22
values[22]	9743	1			T413	29		T741	3		T398	19
values[23]	9624	1			T413	20		T741	3		T398	26
values[24]	9444	1			T413	41		T741	3		T398	31
values[25]	9193	1			T413	28		T741	3		T398	39
values[26]	8753	1			T413	29		T741	3		T398	28
values[27]	8220	1			T413	44		T741	3		T398	21
values[28]	7845	1			T413	38		T741	3		T398	23
values[29]	7467	1			T413	30		T741	3		T398	24
values[30]	7010	1			T413	19		T741	3		T398	17
values[31]	6626	1			T413	21		T741	3		T398	17
values[32]	6154	1			T413	19		T741	3		T398	17
values[33]	5601	1			T413	21		T741	3		T398	11
values[34]	5185	1			T413	13		T741	3		T398	9
values[35]	4813	1			T413	12		T741	3		T398	17
values[36]	4488	1			T413	17		T741	3		T398	23
values[37]	4412	1			T413	22		T741	3		T398	8
values[38]	4169	1			T413	28		T741	3		T398	7
values[39]	4014	1			T413	37		T741	3		T398	5
values[40]	3823	1			T413	22		T741	3		T398	7
values[41]	3712	1			T413	16		T741	3		T398	7
values[42]	3717	1			T413	29		T741	4		T398	8
values[43]	3601	1			T413	24		T741	3		T398	13
values[44]	3599	1			T413	17		T741	3		T398	3
values[45]	3368	1			T413	20		T741	4		T398	4
values[46]	3327	1			T413	18		T741	3		T398	4
values[47]	3324	1			T413	27		T741	3		T398	4
values[48]	3269	1			T413	29		T741	3		T398	8
values[49]	3197	1			T413	24		T741	3		T398	9
values[50]	3149	1			T413	22		T741	3		T398	6
values[51]	3065	1			T413	24		T741	3		T398	10
values[52]	3054	1			T413	21		T741	3		T398	9
values[53]	2891	1			T413	13		T741	3		T398	5
values[54]	2828	1			T413	20		T741	3		T398	6
values[55]	2904	1			T413	21		T741	3		T398	7
values[56]	2828	1			T413	26		T741	3		T398	5
values[57]	2746	1			T413	26		T741	3		T398	5
values[58]	2657	1			T413	24		T741	3		T398	9
values[59]	2651	1			T413	19		T741	3		T398	4
values[60]	2729	1			T413	16		T741	3		T398	2
values[61]	3029	1			T413	18		T741	3		T398	6
values[62]	4633	1			T413	35		T741	3		T398	9
values[63]	17153	1			T413	172		T741	59		T398	33
values[64]	242160	1			T413	437		T741	522		T398	100

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4860902	1			T68	105		T69	490		T70	456
values[2]	804566	1			T68	36		T69	133		T70	22
values[3]	77943	1			T76	8		T75	68		T414	10
values[4]	14141	1			T76	3		T75	1		T414	2
values[5]	5545	1			T76	1		T414	1		T503	16
values[6]	3352	1			T503	6		T413	4		T514	2
values[7]	2545	1			T503	3		T413	7		T514	1
values[8]	2194	1			T503	1		T413	6		T741	2
values[9]	2027	1			T503	1		T413	6		T741	1
values[10]	1772	1			T413	5		T741	1		T398	22
values[11]	1645	1			T413	6		T741	1		T398	25
values[12]	1599	1			T413	4		T741	1		T398	30
values[13]	1450	1			T413	4		T741	1		T398	19
values[14]	1345	1			T413	3		T741	1		T398	22
values[15]	1187	1			T413	5		T741	1		T398	11
values[16]	1185	1			T413	4		T741	1		T398	9
values[17]	1111	1			T413	9		T741	1		T398	6
values[18]	947	1			T413	4		T741	1		T398	4
values[19]	900	1			T413	4		T741	1		T398	10
values[20]	882	1			T413	9		T741	1		T398	11
values[21]	815	1			T413	9		T741	1		T398	9
values[22]	776	1			T413	11		T741	1		T398	2
values[23]	673	1			T413	5		T741	1		T398	1
values[24]	709	1			T413	8		T741	1		T398	1
values[25]	672	1			T413	8		T741	1		T398	1
values[26]	697	1			T413	7		T741	1		T398	1
values[27]	688	1			T413	7		T741	1		T398	6
values[28]	682	1			T413	8		T741	1		T398	5
values[29]	672	1			T413	8		T741	1		T398	10
values[30]	679	1			T413	11		T741	1		T398	1
values[31]	652	1			T413	3		T741	1		T398	1
values[32]	683	1			T413	4		T741	1		T398	1
values[33]	632	1			T413	8		T741	1		T398	2
values[34]	563	1			T413	7		T741	1		T398	1
values[35]	553	1			T413	6		T741	1		T398	3
values[36]	539	1			T413	12		T741	2		T398	3
values[37]	490	1			T413	18		T741	1		T398	1
values[38]	524	1			T413	7		T741	1		T398	1
values[39]	502	1			T413	14		T741	1		T398	2
values[40]	492	1			T413	10		T741	1		T398	1
values[41]	491	1			T413	4		T741	1		T398	1
values[42]	469	1			T413	5		T741	1		T398	2
values[43]	426	1			T413	4		T741	1		T398	2
values[44]	427	1			T413	4		T741	1		T398	1
values[45]	454	1			T413	7		T741	1		T398	2
values[46]	392	1			T413	7		T741	1		T398	1
values[47]	460	1			T413	5		T741	1		T398	1
values[48]	415	1			T413	5		T741	1		T398	2
values[49]	405	1			T413	4		T741	1		T398	3
values[50]	385	1			T413	8		T741	1		T398	1
values[51]	365	1			T413	4		T741	1		T398	1
values[52]	360	1			T413	3		T741	1		T398	1
values[53]	359	1			T413	3		T741	1		T398	1
values[54]	339	1			T413	3		T741	1		T398	1
values[55]	367	1			T413	6		T741	1		T398	1
values[56]	337	1			T413	5		T741	1		T398	1
values[57]	346	1			T413	4		T741	1		T398	1
values[58]	352	1			T413	9		T741	1		T398	1
values[59]	342	1			T413	3		T741	1		T398	2
values[60]	344	1			T413	8		T741	1		T398	3
values[61]	373	1			T413	11		T741	1		T398	1
values[62]	711	1			T413	32		T741	1		T398	2
values[63]	3079	1			T413	153		T741	1		T398	4
values[64]	25900	1			T413	241		T741	193		T398	2

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	629685	1			T68	1		T69	4		T70	71
values[2]	2651018	1			T68	102		T69	439		T70	169
values[3]	1173468	1			T68	60		T69	125		T70	202
values[4]	148648	1			T76	1		T75	125		T412	67
values[5]	74994	1			T75	72		T412	27		T503	8
values[6]	48695	1			T75	43		T412	22		T413	107
values[7]	36437	1			T75	22		T412	28		T413	84
values[8]	29383	1			T75	27		T412	15		T413	58
values[9]	25015	1			T75	15		T412	5		T413	71
values[10]	22298	1			T75	5		T412	9		T413	54
values[11]	19643	1			T75	5		T412	13		T413	52
values[12]	18195	1			T75	1		T412	14		T413	72
values[13]	16999	1			T75	1		T412	5		T413	86
values[14]	15823	1			T75	1		T412	2		T413	77
values[15]	15334	1			T75	3		T412	7		T413	52
values[16]	14804	1			T75	5		T412	3		T413	58
values[17]	14335	1			T412	5		T413	71		T741	3
values[18]	13845	1			T412	8		T413	87		T741	3
values[19]	13204	1			T412	3		T413	89		T741	3
values[20]	12720	1			T413	44		T741	3		T398	15
values[21]	11895	1			T413	33		T741	3		T398	17
values[22]	11725	1			T413	37		T741	3		T398	13
values[23]	11071	1			T413	27		T741	3		T398	12
values[24]	10940	1			T413	16		T741	3		T398	13
values[25]	10335	1			T413	15		T741	4		T398	14
values[26]	9958	1			T413	28		T741	3		T398	14
values[27]	9542	1			T413	22		T741	3		T398	11
values[28]	8945	1			T413	15		T741	3		T398	14
values[29]	8370	1			T413	22		T741	3		T398	22
values[30]	7944	1			T413	20		T741	3		T398	17
values[31]	7408	1			T413	22		T741	3		T398	34
values[32]	6785	1			T413	18		T741	3		T398	18
values[33]	6193	1			T413	18		T741	3		T398	16
values[34]	5742	1			T413	27		T741	3		T398	17
values[35]	5264	1			T413	19		T741	3		T398	10
values[36]	4961	1			T413	22		T741	3		T398	11
values[37]	4719	1			T413	22		T741	3		T398	11
values[38]	4569	1			T413	17		T741	3		T398	11
values[39]	4379	1			T413	18		T741	3		T398	13
values[40]	4367	1			T413	23		T741	3		T398	16
values[41]	4097	1			T413	18		T741	3		T398	11
values[42]	4078	1			T413	19		T741	3		T398	8
values[43]	3943	1			T413	21		T741	3		T398	18
values[44]	3777	1			T413	15		T741	3		T398	18
values[45]	3776	1			T413	9		T741	3		T398	9
values[46]	3685	1			T413	8		T741	3		T398	11
values[47]	3763	1			T413	18		T741	3		T398	16
values[48]	3668	1			T413	18		T741	3		T398	9
values[49]	3561	1			T413	20		T741	3		T398	8
values[50]	3519	1			T413	23		T741	3		T398	20
values[51]	3479	1			T413	14		T741	3		T398	18
values[52]	3217	1			T413	12		T741	3		T398	15
values[53]	3259	1			T413	21		T741	3		T398	23
values[54]	3132	1			T413	15		T741	3		T398	14
values[55]	3163	1			T413	17		T741	3		T398	5
values[56]	3127	1			T413	18		T741	3		T398	5
values[57]	3070	1			T413	17		T741	3		T398	7
values[58]	2947	1			T413	19		T741	3		T398	3
values[59]	2949	1			T413	11		T741	3		T398	5
values[60]	3044	1			T413	20		T741	3		T398	8
values[61]	3114	1			T413	19		T741	3		T398	6
values[62]	4403	1			T413	54		T741	3		T398	14
values[63]	19930	1			T413	232		T741	3		T398	40
values[64]	228160	1			T413	409		T741	579		T398	97