Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2090791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

22518773

1

T1

21416

T2

18279

T3

18344

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15909769	1			T1	8604		T2	9320		T3	14566
values[0x0]	7325026	1			T1	12812		T2	8959		T3	3778
values[0x1]	1374769	1			T1	1464		T2	722		T3	4061

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	758178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23851386

1

T1

22880

T2

19001

T3

22405

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11021816	1			T1	11440		T2	9501		T3	11203
valid_sources[0x01]	11021801	1			T1	11440		T2	9500		T3	11202
valid_sources[0x02]	41024	1			T71	2		T74	1		T135	158
valid_sources[0x03]	40995	1			T71	2		T73	39		T74	1
valid_sources[0x04]	41184	1			T71	2		T380	1		T135	155
valid_sources[0x05]	41177	1			T71	2		T216	1		T135	194
valid_sources[0x06]	41198	1			T71	3		T380	2		T135	165
valid_sources[0x07]	40432	1			T216	1		T380	1		T135	125
valid_sources[0x08]	41248	1			T74	1		T380	2		T135	150
valid_sources[0x09]	44221	1			T71	1		T74	1		T135	215
valid_sources[0x0a]	40394	1			T216	1		T380	1		T135	225
valid_sources[0x0b]	40521	1			T135	179		T335	99		T136	816
valid_sources[0x0c]	41438	1			T135	138		T335	75		T136	841
valid_sources[0x0d]	40626	1			T74	1		T380	2		T135	133
valid_sources[0x0e]	41644	1			T71	1		T74	1		T135	114
valid_sources[0x0f]	41138	1			T135	184		T335	106		T136	787
valid_sources[0x10]	40738	1			T71	1		T216	1		T380	1
valid_sources[0x11]	40365	1			T74	2		T380	1		T135	153
valid_sources[0x12]	41415	1			T71	1		T74	4		T380	2
valid_sources[0x13]	40829	1			T71	1		T216	1		T135	143
valid_sources[0x14]	41481	1			T74	2		T216	3		T135	172
valid_sources[0x15]	41146	1			T380	2		T135	171		T335	130
valid_sources[0x16]	41894	1			T74	1		T216	1		T135	173
valid_sources[0x17]	41621	1			T71	2		T216	2		T380	1
valid_sources[0x18]	42241	1			T74	1		T135	135		T335	132
valid_sources[0x19]	41672	1			T74	1		T380	1		T135	151
valid_sources[0x1a]	41387	1			T216	1		T380	1		T135	105
valid_sources[0x1b]	41586	1			T71	1		T74	2		T135	180
valid_sources[0x1c]	41928	1			T74	1		T135	180		T335	91
valid_sources[0x1d]	41225	1			T71	2		T74	2		T216	2
valid_sources[0x1e]	41841	1			T216	3		T380	1		T135	138
valid_sources[0x1f]	41952	1			T71	1		T135	163		T335	143
valid_sources[0x20]	41472	1			T71	1		T216	2		T380	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15014553

1

T1

8604

T2

9320

T3

14566

values[0x0]

all_enables

biggest_size

7286601

1

T1

12812

T2

8959

T3

3778

values[0x1]

all_enables

biggest_size

217619

1

T71

23

T73

19

T74

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2959974	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469116

1

T68

32

T69

70

T70

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1160396	1			T68	60		T69	185		T70	171
values[0x0]	1108517	1			T68	67		T69	180		T70	187
values[0x1]	1160177	1			T68	70		T69	210		T70	179

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2293764	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1135326

1

T68

79

T69

184

T70

198

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53900	1			T68	2		T69	12		T70	6
valid_sources[0x01]	53354	1			T68	7		T69	13		T70	8
valid_sources[0x02]	53603	1			T68	2		T69	4		T70	10
valid_sources[0x03]	54803	1			T68	9		T69	5		T70	9
valid_sources[0x04]	53104	1			T68	3		T69	12		T70	9
valid_sources[0x05]	53409	1			T68	4		T69	10		T70	4
valid_sources[0x06]	53952	1			T68	3		T69	8		T70	12
valid_sources[0x07]	52815	1			T68	2		T69	9		T70	9
valid_sources[0x08]	53203	1			T68	2		T69	14		T70	12
valid_sources[0x09]	52813	1			T68	1		T69	7		T70	9
valid_sources[0x0a]	52793	1			T69	15		T70	8		T76	1
valid_sources[0x0b]	52803	1			T68	2		T69	13		T70	8
valid_sources[0x0c]	53906	1			T68	5		T69	5		T70	10
valid_sources[0x0d]	54263	1			T68	1		T69	13		T70	5
valid_sources[0x0e]	54040	1			T69	3		T70	14		T76	1
valid_sources[0x0f]	53149	1			T68	4		T69	5		T70	8
valid_sources[0x10]	54053	1			T68	3		T69	18		T70	6
valid_sources[0x11]	52880	1			T68	2		T69	10		T70	13
valid_sources[0x12]	54712	1			T68	3		T69	9		T70	7
valid_sources[0x13]	54054	1			T68	2		T69	6		T70	9
valid_sources[0x14]	54205	1			T68	3		T69	10		T70	6
valid_sources[0x15]	54428	1			T68	3		T69	19		T70	7
valid_sources[0x16]	52818	1			T68	2		T69	9		T70	10
valid_sources[0x17]	52653	1			T68	5		T69	10		T70	14
valid_sources[0x18]	52773	1			T68	1		T69	8		T70	6
valid_sources[0x19]	52635	1			T68	3		T69	10		T70	9
valid_sources[0x1a]	53356	1			T68	6		T69	8		T70	9
valid_sources[0x1b]	53481	1			T68	3		T69	11		T70	7
valid_sources[0x1c]	55312	1			T68	5		T69	8		T70	5
valid_sources[0x1d]	52651	1			T68	2		T69	6		T70	7
valid_sources[0x1e]	53283	1			T68	1		T69	14		T70	9
valid_sources[0x1f]	54075	1			T68	3		T69	8		T70	9
valid_sources[0x20]	52290	1			T68	3		T69	10		T70	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48927

1

T68

1

T69

8

T70

8

values[0x0]

all_enables

biggest_size

370667

1

T68

30

T69

51

T70

62

values[0x1]

all_enables

biggest_size

49522

1

T68

1

T69

11

T70

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3147988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

513423

1

T68

19

T69

82

T70

74

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1251496	1			T68	47		T69	218		T70	158
values[0x0]	1155614	1			T68	47		T69	207		T70	153
values[0x1]	1254301	1			T68	47		T69	198		T70	167

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2416577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1244834

1

T68

51

T69

209

T70

152

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57886	1			T68	4		T69	8		T76	2
valid_sources[0x01]	57742	1			T68	1		T69	5		T70	79
valid_sources[0x02]	57959	1			T68	1		T69	28		T70	49
valid_sources[0x03]	57058	1			T68	1		T69	10		T75	12
valid_sources[0x04]	58127	1			T68	2		T69	6		T76	2
valid_sources[0x05]	57517	1			T68	2		T69	11		T70	49
valid_sources[0x06]	57202	1			T69	18		T76	2		T75	11
valid_sources[0x07]	56175	1			T68	3		T69	3		T70	2
valid_sources[0x08]	57632	1			T69	7		T76	5		T75	8
valid_sources[0x09]	56701	1			T68	1		T69	8		T76	4
valid_sources[0x0a]	56279	1			T68	3		T69	6		T70	6
valid_sources[0x0b]	57523	1			T68	2		T69	2		T76	3
valid_sources[0x0c]	56655	1			T68	1		T69	17		T76	4
valid_sources[0x0d]	56989	1			T68	2		T69	17		T76	2
valid_sources[0x0e]	56472	1			T68	1		T69	18		T70	32
valid_sources[0x0f]	56925	1			T68	1		T69	5		T70	13
valid_sources[0x10]	56957	1			T68	3		T69	2		T76	6
valid_sources[0x11]	56261	1			T68	3		T69	12		T76	2
valid_sources[0x12]	57626	1			T68	2		T69	11		T75	7
valid_sources[0x13]	58295	1			T68	1		T69	11		T76	2
valid_sources[0x14]	58141	1			T68	7		T69	12		T70	20
valid_sources[0x15]	57702	1			T69	18		T75	4		T414	40
valid_sources[0x16]	57481	1			T68	3		T69	17		T75	6
valid_sources[0x17]	56703	1			T68	3		T69	10		T76	1
valid_sources[0x18]	56508	1			T68	3		T69	8		T76	1
valid_sources[0x19]	56329	1			T68	3		T69	10		T70	60
valid_sources[0x1a]	57143	1			T69	15		T75	3		T414	51
valid_sources[0x1b]	57536	1			T68	4		T69	9		T70	6
valid_sources[0x1c]	58590	1			T68	1		T69	14		T76	2
valid_sources[0x1d]	57214	1			T68	3		T69	11		T76	5
valid_sources[0x1e]	57196	1			T68	3		T69	5		T70	31
valid_sources[0x1f]	57550	1			T68	1		T69	11		T76	1
valid_sources[0x20]	57289	1			T68	4		T69	7		T76	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54058

1

T68

1

T69

7

T70

7

values[0x0]

all_enables

biggest_size

405302

1

T68

16

T69

72

T70

63

values[0x1]

all_enables

biggest_size

54063

1

T68

2

T69

3

T70

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2981335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

471799

1

T68

18

T69

78

T70

77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1168110	1			T68	64		T69	189		T70	141
values[0x0]	1116432	1			T68	51		T69	192		T70	172
values[0x1]	1168592	1			T68	48		T69	187		T70	129

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2308453	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1144681

1

T68

46

T69

173

T70

148

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53747	1			T68	2		T69	9		T70	8
valid_sources[0x01]	54268	1			T68	2		T69	18		T70	7
valid_sources[0x02]	54742	1			T68	2		T69	9		T70	5
valid_sources[0x03]	54339	1			T68	5		T69	15		T70	4
valid_sources[0x04]	53716	1			T68	1		T69	3		T70	7
valid_sources[0x05]	53363	1			T68	3		T69	12		T70	9
valid_sources[0x06]	53529	1			T68	2		T69	6		T70	10
valid_sources[0x07]	53511	1			T68	1		T69	8		T70	4
valid_sources[0x08]	53899	1			T68	3		T69	7		T70	9
valid_sources[0x09]	53478	1			T68	1		T69	15		T70	6
valid_sources[0x0a]	52791	1			T68	3		T69	6		T70	11
valid_sources[0x0b]	54873	1			T68	2		T69	18		T70	1
valid_sources[0x0c]	54670	1			T68	1		T69	12		T70	9
valid_sources[0x0d]	54609	1			T68	2		T69	6		T70	5
valid_sources[0x0e]	54259	1			T69	10		T70	9		T76	3
valid_sources[0x0f]	54090	1			T68	3		T69	9		T70	9
valid_sources[0x10]	53712	1			T68	4		T69	8		T70	9
valid_sources[0x11]	53069	1			T68	2		T69	3		T70	12
valid_sources[0x12]	54744	1			T68	1		T69	18		T70	5
valid_sources[0x13]	54802	1			T68	2		T69	8		T70	9
valid_sources[0x14]	54795	1			T68	2		T69	10		T70	7
valid_sources[0x15]	54543	1			T68	3		T69	9		T70	5
valid_sources[0x16]	53906	1			T68	2		T69	7		T70	4
valid_sources[0x17]	53342	1			T68	2		T69	11		T70	5
valid_sources[0x18]	53214	1			T68	1		T69	14		T70	5
valid_sources[0x19]	53745	1			T69	10		T70	5		T75	2
valid_sources[0x1a]	53849	1			T68	3		T69	17		T70	8
valid_sources[0x1b]	53860	1			T68	2		T69	4		T70	2
valid_sources[0x1c]	54280	1			T68	2		T69	14		T70	6
valid_sources[0x1d]	54076	1			T68	3		T69	5		T70	3
valid_sources[0x1e]	54414	1			T69	5		T70	6		T76	1
valid_sources[0x1f]	53595	1			T68	2		T69	7		T70	5
valid_sources[0x20]	53310	1			T68	2		T69	6		T70	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49436

1

T68

1

T69

11

T70

7

values[0x0]

all_enables

biggest_size

372799

1

T68

13

T69

62

T70

67

values[0x1]

all_enables

biggest_size

49564

1

T68

4

T69

5

T70

3