Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	378095863	39671318	0	0
DepthKnown_A	378095863	377999750	0	0
RvalidKnown_A	378095863	377999750	0	0
WreadyKnown_A	378095863	377999750	0	0
gen_passthru_fifo.paramCheckPass	892	892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	39671318	0	0
T1	356797	42497	0	0
T2	421965	52840	0	0
T3	211002	21303	0	0
T4	546795	360807	0	0
T12	102207	12618	0	0
T52	75298	6897	0	0
T56	162267	17014	0	0
T58	248079	32178	0	0
T84	224995	30162	0	0
T85	130101	22489	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	378095863	30318968	0	0
DepthKnown_A	378095863	377999750	0	0
RvalidKnown_A	378095863	377999750	0	0
WreadyKnown_A	378095863	377999750	0	0
gen_passthru_fifo.paramCheckPass	892	892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	30318968	0	0
T1	356797	32626	0	0
T2	421965	44552	0	0
T3	211002	17391	0	0
T4	546795	356477	0	0
T12	102207	9531	0	0
T52	75298	4671	0	0
T56	162267	12807	0	0
T58	248079	22485	0	0
T84	224995	25917	0	0
T85	130101	14843	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	378095863	22576742	0	0
DepthKnown_A	378095863	377999750	0	0
RvalidKnown_A	378095863	377999750	0	0
WreadyKnown_A	378095863	377999750	0	0
gen_passthru_fifo.paramCheckPass	892	892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	22576742	0	0
T1	356797	23439	0	0
T2	421965	19452	0	0
T3	211002	22607	0	0
T4	546795	379259	0	0
T12	102207	6774	0	0
T52	75298	3213	0	0
T56	162267	9576	0	0
T58	248079	16452	0	0
T84	224995	12430	0	0
T85	130101	6734	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	378095863	22081057	0	0
DepthKnown_A	378095863	377999750	0	0
RvalidKnown_A	378095863	377999750	0	0
WreadyKnown_A	378095863	377999750	0	0
gen_passthru_fifo.paramCheckPass	892	892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	22081057	0	0
T1	356797	22880	0	0
T2	421965	19001	0	0
T3	211002	22405	0	0
T4	546795	378528	0	0
T12	102207	6594	0	0
T52	75298	3073	0	0
T56	162267	9312	0	0
T58	248079	16069	0	0
T84	224995	12170	0	0
T85	130101	6461	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378095863	377999750	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455334010	99739	0	0
DepthKnown_A	455334010	455226137	0	0
RvalidKnown_A	455334010	455226137	0	0
WreadyKnown_A	455334010	455226137	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	99739	0	0
T1	356797	72	0	0
T2	421965	60	0	0
T3	211002	53	0	0
T4	546795	27	0	0
T12	102207	22	0	0
T52	75298	19	0	0
T56	162267	27	0	0
T58	248079	151	0	0
T84	224995	31	0	0
T85	130101	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455334010	104208	0	0
DepthKnown_A	455334010	455226137	0	0
RvalidKnown_A	455334010	455226137	0	0
WreadyKnown_A	455334010	455226137	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	104208	0	0
T1	356797	72	0	0
T2	421965	60	0	0
T3	211002	53	0	0
T4	546795	27	0	0
T12	102207	22	0	0
T52	75298	19	0	0
T56	162267	27	0	0
T58	248079	151	0	0
T84	224995	31	0	0
T85	130101	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455334010	48906	0	0
DepthKnown_A	455334010	455226137	0	0
RvalidKnown_A	455334010	455226137	0	0
WreadyKnown_A	455334010	455226137	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	48906	0	0
T1	356797	68	0	0
T2	421965	57	0	0
T3	211002	52	0	0
T4	546795	25	0	0
T12	102207	19	0	0
T52	75298	18	0	0
T56	162267	25	0	0
T58	248079	95	0	0
T84	224995	24	0	0
T85	130101	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455334010	48906	0	0
DepthKnown_A	455334010	455226137	0	0
RvalidKnown_A	455334010	455226137	0	0
WreadyKnown_A	455334010	455226137	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	48906	0	0
T1	356797	68	0	0
T2	421965	57	0	0
T3	211002	52	0	0
T4	546795	25	0	0
T12	102207	19	0	0
T52	75298	18	0	0
T56	162267	25	0	0
T58	248079	95	0	0
T84	224995	24	0	0
T85	130101	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455334010	50833	0	0
DepthKnown_A	455334010	455226137	0	0
RvalidKnown_A	455334010	455226137	0	0
WreadyKnown_A	455334010	455226137	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	50833	0	0
T1	356797	4	0	0
T2	421965	3	0	0
T3	211002	1	0	0
T4	546795	2	0	0
T12	102207	3	0	0
T52	75298	1	0	0
T56	162267	2	0	0
T58	248079	56	0	0
T84	224995	7	0	0
T85	130101	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455334010	55302	0	0
DepthKnown_A	455334010	455226137	0	0
RvalidKnown_A	455334010	455226137	0	0
WreadyKnown_A	455334010	455226137	0	0
gen_passthru_fifo.paramCheckPass	2783	2783	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	55302	0	0
T1	356797	4	0	0
T2	421965	3	0	0
T3	211002	1	0	0
T4	546795	2	0	0
T12	102207	3	0	0
T52	75298	1	0	0
T56	162267	2	0	0
T58	248079	56	0	0
T84	224995	7	0	0
T85	130101	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455334010	455226137	0	0
T1	356797	356574	0	0
T2	421965	421786	0	0
T3	211002	210940	0	0
T4	546795	546778	0	0
T12	102207	102149	0	0
T52	75298	75243	0	0
T56	162267	162158	0	0
T58	248079	247959	0	0
T84	224995	224937	0	0
T85	130101	130050	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2783	2783	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0