Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	INPUT
tl_o.a_ready	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	OUTPUT
tl_o.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	OUTPUT
tl_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T176,*T68,*T69	Yes	T176,T68,T69	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T100,*T175	Yes	T3,T100,T175	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T101,T77,T370	Yes	T101,T77,T370	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T80,T238	Yes	T77,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T80,T81	Yes	T77,T80,T238	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T101,T77,T370	Yes	T101,T77,T370	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T3,T100,T274	Yes	T3,T100,T274	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T100,T175	Yes	T3,T100,T175	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_break_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_timeout_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T41,T278,T186	Yes	T41,T278,T186	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T41,T278,T186	Yes	T41,T278,T186	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T41,T144,T278	Yes	T41,T144,T278	INPUT
tl_o.a_ready	Yes	Yes	T41,T144,T278	Yes	T41,T144,T278	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T75	Yes	T68,T69,T70	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T278,T279,T280	Yes	T278,T279,T280	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T144,T278,T279	Yes	T41,T144,T278	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T144,T278,T279	Yes	T41,T144,T278	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T75	Yes	T69,T70,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T278,*T279,*T280	Yes	T278,T279,T280	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T41,T144,T278	Yes	T41,T144,T278	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T77,T370,T622	Yes	T77,T370,T622	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T80,T81	Yes	T77,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T80,T81	Yes	T77,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T77,T370,T622	Yes	T77,T370,T622	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T278,T279,T280	Yes	T278,T279,T280	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T278,T279,T280	Yes	T278,T279,T280	OUTPUT
intr_rx_watermark_o	Yes	Yes	T278,T279,T280	Yes	T278,T279,T280	OUTPUT
intr_tx_empty_o	Yes	Yes	T278,T279,T280	Yes	T278,T279,T280	OUTPUT
intr_rx_overflow_o	Yes	Yes	T278,T279,T280	Yes	T278,T279,T280	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_break_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_timeout_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	INPUT
tl_o.a_ready	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
tl_o.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
tl_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T274,*T268	Yes	T3,T274,T268	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T101,T77,T144	Yes	T101,T77,T144	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T80,T238	Yes	T77,T81,T410	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T81,T410	Yes	T77,T80,T238	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T101,T77,T144	Yes	T101,T77,T144	OUTPUT
cio_rx_i	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	INPUT
cio_tx_o	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_break_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_timeout_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	INPUT
tl_o.a_ready	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
tl_o.d_error	Yes	Yes	T68,T70,T75	Yes	T68,T70,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
tl_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T100,*T175,*T304	Yes	T100,T175,T304	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T77,T144,T80	Yes	T77,T144,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T80,T81	Yes	T77,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T80,T81	Yes	T77,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T77,T144,T80	Yes	T77,T144,T80	OUTPUT
cio_rx_i	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	INPUT
cio_tx_o	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
intr_rx_watermark_o	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
intr_tx_empty_o	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
intr_rx_overflow_o	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_break_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_timeout_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	INPUT
tl_o.a_ready	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	OUTPUT
tl_o.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	OUTPUT
tl_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T69,*T70,*T75	Yes	T68,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T13,*T115,*T289	Yes	T13,T115,T289	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T77,T309,T144	Yes	T77,T309,T144	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T77,T80,T81	Yes	T77,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T77,T80,T81	Yes	T77,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T77,T309,T144	Yes	T77,T309,T144	OUTPUT
cio_rx_i	Yes	Yes	T13,T115,T290	Yes	T13,T115,T290	INPUT
cio_tx_o	Yes	Yes	T13,T115,T290	Yes	T13,T115,T290	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	OUTPUT
intr_rx_watermark_o	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_break_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_timeout_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T289,T299,T305	Yes	T289,T299,T305	OUTPUT

*Tests covering at least one bit in the range