Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T70,T76,T75	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T69,T76,T75	Yes	T69,T76,T75	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T1,T58,T181	Yes	T1,T58,T181	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T58,T181	Yes	T1,T58,T181	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T73,T216,T68	Yes	T73,T216,T68	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T73,T216,T68	Yes	T73,T216,T68	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T1,T58,T59	Yes	T1,T58,T59	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T4,T44,T63	Yes	T4,T44,T63	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T4,T44,T63	Yes	T4,T44,T63	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T4,T44,T63	Yes	T4,T44,T63	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T4,T44,T63	Yes	T4,T44,T63	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T44,T63	Yes	T4,T44,T63	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T44,T63,T71	Yes	T44,T63,T71	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T4,*T44,*T63	Yes	T4,T44,T63	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T4,T44,T63	Yes	T4,T44,T63	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T70,T76,T75	Yes	T68,T69,T70	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T69,T70,T75	Yes	T68,T69,T70	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T221,T222,T176	Yes	T221,T222,T176	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T221,T222,T176	Yes	T221,T222,T176	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T221,T222,T176	Yes	T221,T222,T176	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T221,T222,T176	Yes	T221,T222,T176	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T221,T222,T176	Yes	T221,T222,T176	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T221,*T222,*T223	Yes	T221,T222,T223	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T221,T222,T176	Yes	T221,T222,T176	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T56	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T221,T222,T223	Yes	T221,T222,T223	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T221,T222,T176	Yes	T221,T222,T176	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T56	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T221,*T222,*T223	Yes	T221,T222,T223	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T56	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T221,T222,T176	Yes	T221,T222,T176	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T57,T160,T161	Yes	T57,T160,T161	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T196,T400,T271	Yes	T196,T400,T271	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T196,T400,T271	Yes	T196,T400,T271	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T196,T400,T271	Yes	T196,T400,T271	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T196,T400,T271	Yes	T196,T400,T271	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T196,T400,T271	Yes	T196,T400,T271	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T196,T400,T233	Yes	T196,T400,T233	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T53,T54,T55	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T196,T400,T233	Yes	T196,T400,T233	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T68,T69,*T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T196,*T271,*T233	Yes	T196,T400,T271	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T196,T400,T271	Yes	T196,T400,T271	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T315,T181,T309	Yes	T315,T181,T309	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T176,*T68,*T69	Yes	T176,T68,T69	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T9,T179,T180	Yes	T9,T179,T180	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T9,T141,T142	Yes	T9,T141,T142	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T9,T141,T142	Yes	T9,T141,T142	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T9,*T141,*T142	Yes	T9,T141,T142	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T9,T144,T141	Yes	T9,T144,T141	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T176,*T68,*T69	Yes	T176,T68,T69	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T69,T70,T76	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T31,*T141,*T142	Yes	T31,T141,T142	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T31,T141,T142	Yes	T31,T141,T142	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T15,T93,T53	Yes	T15,T93,T53	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T15,T93,T53	Yes	T15,T93,T53	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T15,T93,T53	Yes	T15,T93,T53	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T15,T93,T53	Yes	T15,T93,T53	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T15,T53,T16	Yes	T15,T53,T16	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T15,T93,T53	Yes	T15,T93,T53	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T15,T93,T53	Yes	T15,T93,T53	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T15,T93,T53	Yes	T15,T93,T53	INPUT
tl_usbdev_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T93,T17,T289	Yes	T93,T17,T289	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T93,T65,T17	Yes	T93,T65,T17	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T15,T93,T53	Yes	T15,T93,T17	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T68,T69,T76	Yes	T68,T69,T70	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T15,*T93,*T53	Yes	T15,T93,T17	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T15,T93,T53	Yes	T15,T93,T53	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T69,T70	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T56	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T56	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T69,T70	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T71,T68,T69	Yes	T71,T68,T69	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T71,T68,T69	Yes	T71,T68,T69	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T71,T68,T69	Yes	T71,T68,T69	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T71,T68,T69	Yes	T71,T68,T69	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T71,T68,T69	Yes	T71,T68,T69	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T71,T68,T69	Yes	T71,T68,T69	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T71,T68,T69	Yes	T71,T68,T69	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T71,T70,T76	Yes	T71,T68,T69	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T71,T68,T69	Yes	T71,T68,T69	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T68,T69	Yes	T71,T68,T69	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T71,T69,T70	Yes	T71,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T71,T69,T70	Yes	T71,T68,T69	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T71,*T68,*T69	Yes	T71,T68,T69	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T71,T68,T69	Yes	T71,T68,T69	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T3,T52	Yes	T1,T3,T52	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T56	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T71,*T68,*T69	Yes	T71,T68,T69	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T348,T317,T259	Yes	T348,T317,T259	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	INPUT
tl_hmac_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	INPUT
tl_hmac_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T68,T69	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T348,*T41,*T71	Yes	T348,T41,T71	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T348,T41,T71	Yes	T348,T41,T71	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T182,T71,T110	Yes	T182,T71,T110	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T71,T110,T266	Yes	T71,T110,T266	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T71,*T68,*T69	Yes	T71,T68,T69	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T110,T266,T267	Yes	T110,T266,T267	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	INPUT
tl_kmac_i.d_error	Yes	Yes	T69,T70,T75	Yes	T69,T70,T76	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T109,T182,T71	Yes	T71,T157,T110	INPUT
tl_kmac_i.d_sink	Yes	Yes	T69,T70,T75	Yes	T69,T70,T76	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T69,T70	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T69,T70,T76	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T109,*T182,*T71	Yes	T71,T157,T110	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T102,T109,T640	Yes	T102,T109,T640	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T102,T109,T640	Yes	T102,T109,T640	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T102,T109,T316	Yes	T102,T109,T316	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T102,T109,T640	Yes	T102,T109,T640	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T102,T109,T316	Yes	T102,T109,T316	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T73,*T69,*T70	Yes	T73,T69,T70	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T70,T76,T75	Yes	T70,T76,T75	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T102,T109,T316	Yes	T102,T109,T316	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T102,T109,T316	Yes	T102,T109,T316	INPUT
tl_aes_i.d_error	Yes	Yes	T68,T69,T70	Yes	T69,T70,T76	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T102,T109,T316	Yes	T102,T109,T316	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T102,T109,T640	Yes	T102,T109,T640	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T102,T316,T640	Yes	T102,T109,T316	INPUT
tl_aes_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T73,*T68,*T69	Yes	T73,T69,T70	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T102,*T109,*T316	Yes	T102,T109,T316	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T102,T109,T316	Yes	T102,T109,T316	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T71,*T68,*T69	Yes	T71,T68,T69	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T71,*T68,*T69	Yes	T71,T68,T69	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T119,*T118,*T109	Yes	T119,T118,T41	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T71,*T73,*T68	Yes	T71,T73,T68	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T71,*T73,*T68	Yes	T71,T73,T68	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T119,*T118,*T109	Yes	T119,T118,T109	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T71,*T68,*T69	Yes	T71,T68,T69	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T69,T70,T76	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T68,T69	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T69,T70,T75	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T119,*T118,*T109	Yes	T119,T118,T109	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T71,*T68,*T69	Yes	T71,T68,T69	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	INPUT
tl_edn1_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	INPUT
tl_edn1_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T68,T69	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T119,*T118,*T109	Yes	T119,T118,T109	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T119,T118,T109	Yes	T119,T118,T109	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T12,T58	Yes	T3,T12,T58	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T12,T85	Yes	T3,T12,T85	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T12,T85	Yes	T3,T12,T85	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T12,T85	Yes	T3,T12,T85	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T12,T85	Yes	T3,T12,T85	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T176,*T68,*T69	Yes	T176,T68,T69	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T12,T85	Yes	T3,T12,T85	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T12,T85	Yes	T3,T12,T85	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T58,T100	Yes	T3,T58,T100	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T12,T85	Yes	T3,T12,T85	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T12,T85	Yes	T3,T12,T85	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T12,*T85	Yes	T3,T12,T85	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T12,T85	Yes	T3,T12,T85	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T74,*T216,*T380	Yes	T74,T216,T380	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	INPUT
tl_otbn_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	INPUT
tl_otbn_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T74,*T216,*T380	Yes	T74,T216,T380	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T118,*T41,*T109	Yes	T118,T41,T109	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T118,T41,T109	Yes	T118,T41,T109	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T41,T109,T182	Yes	T41,T109,T182	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T41,T109,T182	Yes	T41,T109,T182	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T41,T109,T182	Yes	T41,T109,T182	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T41,T109,T182	Yes	T41,T109,T182	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T71,*T68,*T69	Yes	T71,T68,T69	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T41,T109,T182	Yes	T41,T109,T182	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T41,T109,T182	Yes	T41,T109,T182	INPUT
tl_keymgr_i.d_error	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T109,T182,T71	Yes	T109,T182,T71	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T109,T182	Yes	T41,T109,T182	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T41,T109,T182	Yes	T41,T109,T182	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T68,T69	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T41,*T109,*T182	Yes	T41,T109,T182	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T41,T109,T182	Yes	T41,T109,T182	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T12,T85,T58	Yes	T12,T85,T58	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T12,T85,T58	Yes	T12,T85,T58	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T75	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T41,T165	Yes	T1,T41,T165	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T41,T210	Yes	T1,T41,T210	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T41,T210	Yes	T1,T41,T210	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T1,T41,T165	Yes	T1,T41,T165	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T1,T41,T210	Yes	T1,T41,T210	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T176,*T68,*T69	Yes	T176,T68,T69	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T1,T41,T210	Yes	T1,T41,T210	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T1,T41,T210	Yes	T1,T41,T210	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T1,T168,T272	Yes	T1,T168,T272	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T165,T111	Yes	T1,T41,T165	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T1,T165,T111	Yes	T1,T41,T165	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T176,*T68,*T69	Yes	T176,T68,T69	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T1,*T165,*T111	Yes	T1,T210,T165	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T1,T41,T210	Yes	T1,T41,T210	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T56	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range