dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[1].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[2].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[5].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[8].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[9].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[10].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[11].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[12].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[13].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[14].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[15].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[16].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[17].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[18].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[19].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[20].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[21].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[22].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[0].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[1].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[2].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[3].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[4].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[5].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT6,T17,T22
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT6,T15,T16
01CoveredT28,T29,T30
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT17,T22,T8

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT6,T15,T16
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T22,T8

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT17,T22,T8

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T22,T8
11CoveredT28,T29,T30

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T17,T22,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T17,T22
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT6,T65,T17
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT6,T17,T22

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T17,T22

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT6,T17,T22

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T17,T22
11CoveredT28,T29,T30

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T6,T17,T22
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3900
CONT_ASSIGN9800
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
98 unreachable
103 1 1
104 1 1


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3900
CONT_ASSIGN9800
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
98 unreachable
103 1 1
104 1 1


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT71,T9,T6
01CoveredT9,T6,T31
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT9,T7,T10
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T34
11CoveredT9,T7,T10

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T34

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT9,T7,T10
11CoveredT28,T29,T34

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T7,T10

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T34
11CoveredT9,T7,T10

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T34
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T7,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T9,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT71,T9,T73
01CoveredT9,T6,T31
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT9,T6,T7
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T34
11CoveredT6,T7,T8

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT6,T7,T8
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T7,T8

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT6,T7,T8

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T9,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT71,T9,T73
01CoveredT9,T6,T31
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT9,T6,T7
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T30,T34
11CoveredT6,T7,T8

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T34

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT6,T7,T8
11CoveredT28,T29,T34

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T7,T8

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T34
11CoveredT6,T7,T8

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T34
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T9,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT71,T9,T73
01CoveredT9,T6,T31
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT9,T6,T8
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T34
11CoveredT6,T7,T8

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT6,T7,T8
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T7,T8

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT6,T7,T8

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T31,T32

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T9,T31,T32
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT71,T9,T6
01CoveredT9,T31,T32
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT9,T10,T8
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT9,T6,T10

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT9,T6,T10
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T6,T10

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT9,T6,T10

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T6,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT71,T9,T6
01CoveredT9,T6,T31
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT9,T6,T7
01CoveredT28,T29,T30
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT9,T10,T11

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT9,T6,T7
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT9,T10,T11
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT9,T10,T11

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T38,T39
01CoveredT4,T38,T39
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT9,T7,T10
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T30,T34
11CoveredT9,T7,T10

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT9,T7,T10
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T7,T10

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT9,T7,T10

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T7,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T38,T39
01CoveredT4,T38,T39
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT4,T38,T39
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT4,T38,T39

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT4,T38,T39
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T38,T39

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT4,T38,T39

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T4,T38,T39
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T38,T39
01CoveredT9,T6,T7
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT9,T6,T10
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT9,T6,T8

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT9,T6,T8
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T6,T8

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT9,T6,T8

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T6,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T38,T39
01CoveredT9,T6,T7
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT9,T6,T10
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT9,T6,T8

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT9,T6,T8
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T6,T8

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT9,T6,T8

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T6,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3900
CONT_ASSIGN5300
CONT_ASSIGN6011100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
53 unreachable
60 1 1
62 1 1
67 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       62
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T38,T39
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       67
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 60 1 1 100.00
TERNARY 67 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 67 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3900
CONT_ASSIGN5300
CONT_ASSIGN6011100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
53 unreachable
60 1 1
62 1 1
67 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       62
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T9,T72
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       67
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 60 1 1 100.00
TERNARY 67 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 67 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT45,T19,T20
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT19,T20,T8
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT45,T7,T50
10CoveredT28,T29,T30
11CoveredT1,T2,T3

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT35,T36,T37

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT35,T36,T37

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT45,T7,T50
1CoveredT1,T2,T3

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT45,T7,T50
10CoveredT28,T29,T30
11CoveredT1,T2,T3

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T45,T7,T50


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT35,T6,T45
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT35,T19,T20
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT6,T45,T50
10CoveredT35,T36,T37
11CoveredT1,T2,T3

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT35,T36,T37
01CoveredT1,T2,T3
10CoveredT35,T36,T37

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT35,T36,T37
11CoveredT35,T36,T37

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T30,T34

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT1,T2,T3
11CoveredT29,T30,T34

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT35,T6,T45
1CoveredT1,T2,T3

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT35,T6,T45
10CoveredT29,T30,T34
11CoveredT1,T2,T3

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T29,T30,T34
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T35,T6,T45


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT12,T13,T14
01CoveredT12,T13,T14
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT12,T14,T24
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T14,T24

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT12,T14,T24
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T14,T24

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T14,T24

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T12,T14,T24
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT12,T13,T14
01CoveredT12,T13,T14
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT12,T13,T14
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T13,T14

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT12,T13,T14
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T13,T14

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T13,T14

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T12,T13,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT12,T84,T14
01CoveredT12,T84,T14
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT12,T84,T14
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T84,T14

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT12,T84,T14
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T84,T14

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T84,T14

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T12,T84,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT12,T14,T71
01CoveredT12,T14,T6
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT12,T14,T24
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T14,T24

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT12,T14,T24
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T14,T24

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T14,T24

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T12,T14,T24
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT12,T100,T175
01CoveredT12,T100,T175
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT12,T14,T6
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T14,T6

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT12,T14,T6
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T14,T6

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T14,T6

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T12,T14,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3900
CONT_ASSIGN7411100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
74 1 1
76 1 1
80 1 1
81 1 1
88 1 1
89 1 1
91 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3030100.00
Logical3030100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT12,T100,T175
01CoveredT12,T100,T175
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T29,T30
10CoveredT12,T100,T175
11CoveredT28,T29,T30

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T100,T175

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT28,T29,T30
01CoveredT1,T2,T3
10CoveredT28,T29,T30

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT28,T29,T30

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT28,T29,T30
10CoveredT12,T100,T175
11CoveredT28,T29,T30

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T100,T175

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T30
11CoveredT12,T100,T175

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 74 1 1 100.00
TERNARY 88 2 2 100.00
TERNARY 89 2 2 100.00
TERNARY 91 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 74 (ie_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 88 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T12,T100,T175
0 Covered T1,T2,T3


LineNo. Expression -1-: 91 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T28,T29,T30
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 892 892 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 892 892 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T12 1 1 0 0
T52 1 1 0 0
T56 1 1 0 0
T58 1 1 0 0
T84 1 1 0 0
T85 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%