Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	92.83		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T315,T181,T309	Yes	T315,T181,T309	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T41,T278,T186	Yes	T41,T278,T186	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T41,T278,T186	Yes	T41,T278,T186	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T41,T144,T278	Yes	T41,T144,T278	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T41,T144,T278	Yes	T41,T144,T278	INPUT
tl_uart0_i.d_error	Yes	Yes	T69,T70,T75	Yes	T68,T69,T70	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T278,T279,T280	Yes	T278,T279,T280	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T144,T278,T279	Yes	T41,T144,T278	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T144,T278,T279	Yes	T41,T144,T278	INPUT
tl_uart0_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T69,T70,T75	Yes	T69,T70,T75	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T278,*T279,*T280	Yes	T278,T279,T280	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T41,T144,T278	Yes	T41,T144,T278	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	INPUT
tl_uart1_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	INPUT
tl_uart1_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T3,*T274,*T268	Yes	T3,T274,T268	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T3,T274,T268	Yes	T3,T274,T268	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	INPUT
tl_uart2_i.d_error	Yes	Yes	T68,T70,T75	Yes	T68,T70,T75	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	INPUT
tl_uart2_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T100,*T175,*T304	Yes	T100,T175,T304	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T100,T175,T304	Yes	T100,T175,T304	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	INPUT
tl_uart3_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T13,T115,T289	Yes	T13,T115,T289	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	INPUT
tl_uart3_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T75	Yes	T68,T69,T70	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T13,*T115,*T289	Yes	T13,T115,T289	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T13,T115,T144	Yes	T13,T115,T144	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T71,T297,T288	Yes	T71,T297,T288	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T71,T297,T288	Yes	T71,T297,T288	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T71,T144,T297	Yes	T71,T144,T297	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T71,T144,T297	Yes	T71,T144,T297	INPUT
tl_i2c0_i.d_error	Yes	Yes	T69,T70,T75	Yes	T69,T70,T75	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T71,T297,T288	Yes	T71,T297,T288	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T144,T297	Yes	T71,T144,T297	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T71,T144,T297	Yes	T71,T144,T297	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T69,T70,T75	Yes	T68,T69,T70	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T68,T69	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T71,*T297,*T288	Yes	T71,T297,T288	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T71,T144,T297	Yes	T71,T144,T297	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T275,T71,T288	Yes	T275,T71,T288	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T275,T71,T288	Yes	T275,T71,T288	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T275,T71,T144	Yes	T275,T71,T144	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T275,T71,T144	Yes	T275,T71,T144	INPUT
tl_i2c1_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T275,T71,T288	Yes	T275,T71,T288	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T275,T71,T144	Yes	T275,T71,T144	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T275,T71,T144	Yes	T275,T71,T144	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T68,T69	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T68,T69,T75	Yes	T68,T69,T75	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T275,*T71,*T288	Yes	T275,T71,T288	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T275,T71,T144	Yes	T275,T71,T144	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T71,T288,T307	Yes	T71,T288,T307	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T71,T288,T307	Yes	T71,T288,T307	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T71,T144,T288	Yes	T71,T144,T288	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T71,T144,T288	Yes	T71,T144,T288	INPUT
tl_i2c2_i.d_error	Yes	Yes	T69,T75,T345	Yes	T69,T75,T345	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T71,T288,T307	Yes	T71,T288,T307	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T144,T288	Yes	T71,T144,T288	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T71,T144,T288	Yes	T71,T144,T288	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T69,T70,T75	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T71,*T69,*T70	Yes	T71,T68,T69	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T69,T70,T75	Yes	T68,T69,T70	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T71,*T288,*T307	Yes	T71,T288,T307	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T71,T144,T288	Yes	T71,T144,T288	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T141,T142,T143	Yes	T141,T142,T143	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T141,T142,T143	Yes	T141,T142,T143	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T141,T142,T53	Yes	T141,T142,T53	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T141,T142,T53	Yes	T141,T142,T53	INPUT
tl_pattgen_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T141,T142,T143	Yes	T141,T142,T143	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T141,T142,T143	Yes	T141,T142,T53	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T141,T142,T143	Yes	T141,T142,T53	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T69,T70,*T75	Yes	T68,T69,T70	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T141,*T142,*T143	Yes	T141,T142,T143	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T141,T142,T53	Yes	T141,T142,T53	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T84,T276,T277	Yes	T84,T276,T277	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T84,T276,T277	Yes	T84,T276,T277	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T84,T276,T53	Yes	T84,T276,T53	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T84,T276,T53	Yes	T84,T276,T53	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T68,T70,T76	Yes	T68,T70,T76	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T84,T276,T277	Yes	T84,T276,T277	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T84,T276,T277	Yes	T84,T276,T53	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T84,T276,T277	Yes	T84,T276,T53	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T68,T69,T70	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T84,*T276,*T277	Yes	T84,T276,T277	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T84,T276,T53	Yes	T84,T276,T53	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T68,T69,T76	Yes	T68,T69,T70	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T71,T288,T82	Yes	T71,T288,T82	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T288,T82	Yes	T12,T84,T14	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T71,T288,T82	Yes	T12,T84,T14	INPUT
tl_gpio_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T71,*T68,*T69	Yes	T71,T68,T69	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T12	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T4,T38,T39	Yes	T4,T38,T39	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T4,T38,T39	Yes	T4,T38,T39	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T4,T38,T39	Yes	T4,T38,T39	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T4,T38,T39	Yes	T4,T38,T39	INPUT
tl_spi_device_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T4,T38,T39	Yes	T4,T38,T39	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T38,T39	Yes	T4,T38,T39	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T4,T38,T39	Yes	T4,T38,T39	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T4,*T38,*T39	Yes	T4,T38,T39	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T4,T38,T39	Yes	T4,T38,T39	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T52,T84,T276	Yes	T52,T84,T276	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T52,T84,T276	Yes	T52,T84,T276	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T52,T84,T276	Yes	T52,T84,T276	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T52,T84,T276	Yes	T52,T84,T276	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T52,T141,T142	Yes	T52,T141,T142	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T84,T276	Yes	T52,T84,T276	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T52,T84,T276	Yes	T52,T84,T276	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T52,*T84,*T276	Yes	T52,T84,T276	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T52,T84,T276	Yes	T52,T84,T276	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T12,T56	Yes	T2,T12,T56	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T12,T56	Yes	T2,T12,T56	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T2,T12,T56	Yes	T2,T12,T56	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T2,T12,T56	Yes	T2,T12,T56	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T69,T70,T75	Yes	T69,T70,T75	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T12,T56	Yes	T2,T12,T56	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T12,T56	Yes	T2,T12,T56	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T2,T12,T56	Yes	T2,T12,T56	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T75	Yes	T68,T69,T70	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T12,*T56	Yes	T2,T12,T56	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T2,T12,T56	Yes	T2,T12,T56	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T68,T69,T70	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T100,T13	Yes	T3,T100,T13	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T3,T100,T13	Yes	T3,T100,T13	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T100,T13	Yes	T3,T100,T13	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T73,*T69,*T70	Yes	T73,T68,T69	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T3,*T100,*T13	Yes	T3,T100,T13	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T68,T69,T70	Yes	T69,T70,T75	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T75	Yes	T69,T70,T76	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T4,*T72,*T139	Yes	T4,T72,T139	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T84	Yes	T1,T4,T140	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T56	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T56	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T69,T70,T75	Yes	T68,T69,T70	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T56	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T41	Yes	T4,T5,T41	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T113,T150	Yes	T5,T113,T150	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T76	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T221,*T222,*T223	Yes	T221,T222,T223	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T68,T69,T76	Yes	T68,T69,T76	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T121,T133,T124	Yes	T121,T133,T124	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T121,T133,T124	Yes	T121,T133,T124	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T84,T85,T58	Yes	T84,T85,T58	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T84,T85,T58	Yes	T84,T85,T58	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T84,T85,T58	Yes	T84,T85,T58	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T84,T85,T58	Yes	T84,T85,T58	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T69,T70,T75	Yes	T69,T70,T76	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T84,T85,T58	Yes	T84,T85,T58	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T84,T85,T58	Yes	T84,T85,T58	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T84,T85,T58	Yes	T84,T85,T58	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T73,*T69,*T70	Yes	T73,T68,T69	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T84,*T85,*T58	Yes	T84,T85,T58	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T84,T85,T58	Yes	T84,T85,T58	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T41,T165,T406	Yes	T41,T165,T406	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T41,T165,T406	Yes	T41,T165,T406	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T41,T165,T406	Yes	T41,T165,T406	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T41,T165,T406	Yes	T41,T165,T406	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T69,T70,T76	Yes	T69,T70,T75	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T165,T111,T166	Yes	T165,T111,T166	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T165,T111,T166	Yes	T41,T165,T111	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T165,T111,T166	Yes	T41,T165,T111	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T165,*T111,*T166	Yes	T165,T406,T111	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T41,T165,T406	Yes	T41,T165,T406	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T2,T56,T85	Yes	T2,T56,T85	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T2,T56,T85	Yes	T2,T56,T85	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T2,T56,T85	Yes	T2,T56,T85	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T74,*T216,*T380	Yes	T74,T216,T380	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T56,T84	Yes	T2,T56,T84	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T2,T56,T84	Yes	T2,T56,T84	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T2,T56,T84	Yes	T2,T56,T84	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T2,T56,T84	Yes	T2,T56,T84	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T56,T84	Yes	T2,T56,T84	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T56,T84	Yes	T2,T56,T84	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T2,T56,T84	Yes	T2,T56,T84	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T73,*T69,*T70	Yes	T73,T68,T69	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T2,*T56,*T84	Yes	T2,T56,T84	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T2,T56,T84	Yes	T2,T56,T84	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T60,T417	Yes	T2,T60,T417	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T2,T60,T417	Yes	T2,T60,T417	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T2,T60,T417	Yes	T2,T60,T417	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T2,T60,T417	Yes	T2,T60,T417	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T60,T417	Yes	T2,T60,T417	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T60,T417	Yes	T2,T60,T417	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T2,T60,T417	Yes	T2,T60,T417	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T176,*T69,*T70	Yes	T176,T68,T69	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T2,*T60,*T417	Yes	T2,T60,T417	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T2,T60,T417	Yes	T2,T60,T417	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T103,T15,T104	Yes	T103,T15,T104	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T103,T15,T104	Yes	T103,T15,T104	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T103,T15,T104	Yes	T103,T15,T104	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T103,T15,T104	Yes	T103,T15,T104	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T68,T69,T76	Yes	T68,T69,T76	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T103,T15,T104	Yes	T103,T15,T104	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T103,T15,T104	Yes	T103,T15,T104	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T103,T15,T104	Yes	T103,T15,T104	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T68,T69,T76	Yes	T68,T69,T76	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T73,*T68,*T69	Yes	T73,T68,T69	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T103,*T15,*T104	Yes	T103,T15,T104	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T103,T15,T104	Yes	T103,T15,T104	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T72	Yes	T4,T71,T72	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T71,T73,T74	Yes	T71,T73,T74	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T69,T70,T76	Yes	T68,T69,T70	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T75	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T2,T56	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T69,T70,*T76	Yes	T68,T69,T70	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range