Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	892	892	0	0
OutputsKnown_A	94957669	94357781	0	0
gen_no_flops.OutputDelay_A	94957669	94357781	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94957669	94357781	0	0
T1	89325	87103	0	0
T2	102859	102400	0	0
T3	51516	51010	0	0
T4	131450	131349	0	0
T12	27569	27011	0	0
T52	18826	18440	0	0
T56	40585	40182	0	0
T58	60622	60278	0	0
T84	54724	54369	0	0
T85	35780	35478	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94957669	94357781	0	0
T1	89325	87103	0	0
T2	102859	102400	0	0
T3	51516	51010	0	0
T4	131450	131349	0	0
T12	27569	27011	0	0
T52	18826	18440	0	0
T56	40585	40182	0	0
T58	60622	60278	0	0
T84	54724	54369	0	0
T85	35780	35478	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	892	892	0	0
OutputsKnown_A	94957669	94357781	0	0
gen_no_flops.OutputDelay_A	94957669	94357781	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892	892	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T52	1	1	0	0
T56	1	1	0	0
T58	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94957669	94357781	0	0
T1	89325	87103	0	0
T2	102859	102400	0	0
T3	51516	51010	0	0
T4	131450	131349	0	0
T12	27569	27011	0	0
T52	18826	18440	0	0
T56	40585	40182	0	0
T58	60622	60278	0	0
T84	54724	54369	0	0
T85	35780	35478	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94957669	94357781	0	0
T1	89325	87103	0	0
T2	102859	102400	0	0
T3	51516	51010	0	0
T4	131450	131349	0	0
T12	27569	27011	0	0
T52	18826	18440	0	0
T56	40585	40182	0	0
T58	60622	60278	0	0
T84	54724	54369	0	0
T85	35780	35478	0	0